DMA拷贝花费的时间远远超过它应该的时间

你好，我想用PIC32MZ2048EFH064端口上的几个I/O引脚来驱动R2R DAC。DMA的任务是每次计时器2匹配发生时将数据移动到输出，当它工作时，完成该序列所需的时间比它应该的时间长3倍。我很难理解为什么会发生这种情况，并且希望有人能弄清楚为什么，这里是第2段。米I有>1)序列长度是255750个样本(字节)，再细分成930x 275个样本长啁啾。imer还配置有1:1预标度，因此它应该在100MHz/4=25MHz4下滴答。在这个标称滴答速率下，我期望在275/25000000=~11uSec5中完成序列中的每个啁啾。在示波器上，~100ns的过渡宽度看起来是正确的，但是该序列需要花费~3倍的时间才能完成。我已经通过启用REFCLKO验证了内核/SYSCLK在200MHz下运行，因此我不明白为什么会发生这种情况。



      以下为原文

    Hi there,

I'm trying to use a few of the I/O pins on PORTF of the PIC32MZ2048EFH064 to drive an R2R DAC.   The DMA is tasked with moving data to the output every time a timer 2 match occurs, and while it is working it is taking 3x longer than it should to complete the sequence.

I am struggling to understand why this is happening, and in the hopes that someone can shed some light on why, here are the parameters I have>

1) Sequence length is 255750 samples (bytes), subdivided in to 930 x 275 sample long chirps.
2) Nominal tick rate is FCPU/8, in this case 200 MHz / 8 = 25 MHz
3) To achieve the nominal tick rate, PB3DIV is configured to 2 to give 100 MHz, and Timer 2 is configured with PR2=3;
4) The timer is also configured with a 1:1 prescalar so it should tick at 100MHz/4 = 25 MHz
4) At this nominal tick rate I expect to complete each chirp in the sequence in 275/25000000 = ~11 uSec
5) On the oscilloscope the transition widths of ~100 ns look right, but the sequence takes ~3x longer to complete

I have verified that the core/SYSCLK is running at 200 MHz via enabling a REFCLKO so I am stumped as to why  this is happening.

Insights appreciated.