边缘电容多项式的系数

亲爱的戴夫，谢谢你的回复。
让我回答你的问题：其实我没有Dunsmore博士的书，但我认为我应该买它。
不幸的是，大学的VNA不支持TDR选项。
我在编写第一个帖子时犯了大错！
因为短标准由连接到衬底底层的两个通孔结束。
另一方面，套件的负载标准由两个并联的100欧姆电阻器结束，这将给出50欧姆，但我的问题（边缘电容多项式中的大系数）与负载标准无关。
对于消极阶段，是的，这是开放标准。
我也是，我不是这方面的专家，但我认为这样的讨论会增加一点经验。
谢谢戴夫



     以下为原文

  Dear Dave,

Thanks for your reply.
Let me answer your questions:
Actually I don't have the book of Dr Dunsmore, but I think that I should buy it.
Unfortunately, the VNA in the university doesn't support the TDR option.
I made a big mistake in writing the first thread!!! Because the short standard is ended by two vias connected to the bottom layer of the substrate.
On the otherhand, the load standard of the kit is ended by two parallel 100ohm resistors which will give 50 ohm, but my problem (big coefficients in the fringing capacitance polynomial) is not related to the load standard.
For the negative phase, yes, it is for the open standard.
Me too, I'm not an expert in this aspect, but I think that such discussions increases the experience a little bit.

Thanks Dave

> {quote:title=Frequency Lover wrote:}{quote}
> Hi Dave,
> 
> thanks for the document, it gives nice details about TDR using on one hand and about TRL calibration method on the other hand.

At least according to 
http://na.tm.agilent.com/vnahelp/tip17.html
the 8753C which you have does not support TRL calibration. 

Since you say at the end this is an undergraduate student project, some of my comments are aimed to get you thinking about things you should document in a report, and to improve your abilitry for someone who is obviously inexperienced. So don't take them the wrong way. I've supervised a number of B.Sc and M.Sc students over the years, so I have some experience in what is worth adding to reports, and what is not. But I'm not a specialist in this area - in fact my Ph.D. is in medical physics. 

> Unfortunately, Agilent told us that the VNA that we are using is obsolete and can't supply us with the TDR option.

I suspect if you persisted more, you could get it. I will drop you a private message about this - so read your PM. If nothing else, it could be good to add to your undergraduate report that you had tried to get an upgrade but failed and list ways you have failed. If you do succeed, I suspect  the university would be please to get an upgrade!  

> Am sorry because I don't know how to add your comments (in boxes as you do) in order to answer them clearly.

You click the little botton marked with two quotation marks. Then put your comments below the ">" you will see. 

> But concerning your question about other standards, the short standard is simply a microstrip line of 20mm lcngth ended by two vias connected to the bottom ground layer of the substrate. For the load standard, also a MS line but ended by two parallel 100 ohm resistances giving rise to 50 ohm resistance.
> 
> I don't have a problem with these standards because defining the offset delay of the short as 0 ps will fix the reference plane at the end of this standard. Of course, we make port extension in order to obtain 180 deg phase shift. Positive or negative delays will be added for other standards w.r.t the difference with the delay of the short.

This is out of my +confort zone+, so some of what I say might be wrong. But I think the short standard should not be set to zero. Instead you should work out what the offset delay is, which you can do from the port extensions. Then the open standard should be some other offset. 

Note that the offset of your calibartion standards are not zero. So if you measure the HP short calibration standard on your VNA, it will not be a dot on the left unless you add the appropiate offset. When you calibrate with the calibration kit, your calibration is valid at the reference plane of the 3.5 mm connector. 

I guess what you are doing will bascially achieve the same thing, but it means you can't use the port extensions facility in the VNA, as that is tied up to being a constant value due to the need to account for this offset.  If you build the offset into your standard, the issue would not arrise. 
 
As I say, this is outside my confort zone, but at least these might give you some things to think about. 

> The problem is to characterize the open standard which has seven parameters to be defined: four capacitance coefficients (C0 to C3), offset delay (difference with delay of short) that gives monotonically negative phase (161 ps in my case), offset impedance (50 ohm) and the offset loss (calculated after obtaining the delay and the losses of the Thru standard at 1GHz).

The open is more tricky. I believe I have got somwhere now in doing this myself, but are not totally convinced. I am still writing the software for it, but I have not hit the problem you are getting with values for C0, C1, C2 and C3 that't cant be entered. 

But what I did was to check I was able to reproduce the values from the cal kit by measuring the cal kit. I was able to do this reasonably well but only if I ignored the data at low frequencies (under about 700 MHz). I think the issue might be that it is difficult for me to measure the phase angles accuractely the phase angles at low freuqencies, as they are so small. I used an "N" cal kit - I've not tried it with my 3.5 mm cal kit. 


> Actually, I tried to pick other values of offset delay but always having the same problem of big coefficients.

To check your methodology, which is always a good thing to do, I suggest you try this. 

1) Do a full 2-port calibration of your VNA using the HP standards to get the best possible accuracy. That might mean you have to put an adapter to get you a thru connection, as you need that for a full 2-port correction, which is the most accurate. 

2) Measure the standards in your kit. 

3) Try to find the properties of the standards in your kit. 

Those are documented in the kit, but if not can be found at 

http://na.tm.agilent.com/pna/caldefs/PNA/85033DE.htm

If you calibrate with that kit, and yet can't determine the data on the kit, then obviously your methods are wrong. In other words, you should be able to find that C0=49.433, C1=-310.13, C2=23.168, C3=-0.15966. 
Note the offsets delays of your standards are not zero, but  2.92E-11 s. Doing the short will be fairly easy. 

I would not be worried if you get different  values, even if the signs for C1, C2 and C3 are quite different. BUT if you plot the curve for what you get, and for what the kit says, they should be pretty similar. If you get very different values, something is wrong. 

> The calibration kit that I use to calibrate the VNA to the end of the test cables is 85033D (M/F) kit supported by Agilent.

That kit is *not* supported by Agilent - it is obsolete. 

http://www.home.agilent.com/en/pd-1000000584%3Aepsg%3Apro-pn-85033D/calibration-kit-35-mm?cc=US&lc=eng

What is more important is whether that kit is supported by the HP8753C's firmware or not. If you see that model is listed as one of the calibration kits, then that is ok. But if not, you should use a user calibration for that. 

Note, you must change the calibriation kit in the 8753 anyway, if you are using 3.5 mm, as I believe that instrument will default to assuming you are using a 7mm (i.e. APC-7) calibration kit. 

What I have done on my HP 8720D is to save a calibration with the name "UPRESET". That means "user preset", and so comes up with the cal kit defined that I want, and not a default APC-7 one. I'm not sure if the 8753 series supports the UPRESET method, but either way, you must ensure that the calibration kit your VNA is expecting is the one you are connecting, and not some other kit. 

It is worth documenting in your undergraduate report that you have checked this. Do *not* assume just because someone has given you access to a VNA and a calibration kit, that they are suitable. They might have one day been suitable, but someone has upgrade the firmware in the 8753C, and they are no longer suitable. The VNA will probaby default to another kit. 

According to http://na.tm.agilent.com/pna/caldefs/stddefs.html
the 85033D is supported in the firmware of the 8753D, but there are two issues there:

1) You have an older 8753C.
2) The supported kit may change with the firmware version you have. 

I know there are about 5 or 6 differences between the information at http://na.tm.agilent.com/pna/caldefs/stddefs.html on the 872xD, and what it actually in the firmware of my 8720D. My VNA seems to have dropped support for some of the older kits, and added support for some of the newer ones 

Given this is an undergraduate project, you should document things like this in your report. The fact you have actually checked the calibration kit is supported in the firmware of the VNA. 

If you find that kit is not supported, then you will need to define that kit as a user calibration kit. 

> Yes I use F/M and F/F SMA adapters during calibration. So, I think that the reference planes are at the end of these adapters after calibration.

Yes. 

> This is an undergraduate project for characterizing SMD lumped elements, so a microstrip line is indispensable for such measurements and consequently an MS calibration kit that finds the performance of these elements only.
> 
> Anyway, I think that I found the solution of this problem, as I tried to simulate the structure using an EM simulator and found that lines of smaller length will give one resonance in the band and at the same time small C coefficients after port extension and fitting the curve of the fringing capacitance.

I think you should be trying to avoid a structure which is resonate - at least at the range of frequencies which are important to you. 
 
> Regards,
> Have a nice day Dave ;)

You too. It sounds an interesting project. If you don't mind, I'd appreciate you emailing me a copy of your final report once you have submitted it. I'd be interested to read it. 

Dr. David Kirkby  (david.kirkby@onetel.net)

> {quote:title=Frequency Lover wrote:}{quote}

> I really appreciate your comments and take them seriously. You say that you are not a specialist in this area, but for me, you are giving valuable information. 

Glad to help where I can. 

> > I suspect if you persisted more, you could get it. I will drop you a private message about this - so read your PM. If nothing else, it could be good to add to your undergraduate report that you had tried to get an upgrade but failed and list ways you have failed. If you do succeed, I suspect  the university would be please to get an upgrade!  
> 
> Yes you are all right; we’ll try to persist more. Maybe the university should communicate Agilent directly.

You might try asking one of the Agilent employees here for advice. You can see they have a blue logo by their name. They fact you are a non-commerical organisation, they are more likely to help than if you were a company. 

> Yes, there is an offset delay for the short standard of HP calibration kit because the measurement plane should be referenced at the end of the 3.5mm SMA connector, so a correction delay should be introduced to return the plane back to the connector end.

Well, the reference plane for 3.5 mm will not be the *very* end of the connector. I suspect it might be the end of the dielectric, but are not sure. I think it is the same place for male and female in 3.5 mm, whereas in N there is a large offset. The location of the reference plane is someting you can check out yourself. 

> But in the case of microstrip calibration kit, we want the reference plane to be at the end of the short microstrip standard, so the offset is set to zero. But this latter idea may be wrong. That is, as you said, I should think about the real value of the offset delay of the short.

OK, I see where you are coming from. 

> > The open is more tricky. I believe I have got somwhere now in doing this myself, but are not totally convinced. I am still writing the software for it, but I have not hit the problem you are getting with values for C0, C1, C2 and C3 that't cant be entered. 
> > 
> > But what I did was to check I was able to reproduce the values from the cal kit by measuring the cal kit. I was able to do this reasonably well but only if I ignored the data at low frequencies (under about 700 MHz). I think the issue might be that it is difficult for me to measure the phase angles accuractely the phase angles at low freuqencies, as they are so small. I used an "N" cal kit - I've not tried it with my 3.5 mm cal kit. 
> > 
> 
> That is a good idea to validate the procedure of extracting the coefficients; I think that I’ll try this.

It's always a good idea to do these sort of sanity check

http://en.wikipedia.org/wiki/Sanity_testing

Joel mentions only considering C0, or perhaps C0 + C1. That is clearly very logical - at least as a first step. The variation of fringing capacitance with frequency, at least on the coaxial standards, is fairly modest, so checking C0 is about right will get you somewhere sensible. 

> Actually, I have the datasheet of the 85033D (attached to this reply) calibration kit (includes the coefficients you mentioned). I’ll try it as soon as possible and give you the results. The challenge is in the open standard!!. 

I'd plot yourself a graph of fringing capacitance vs frequency of your standards. It would be useful to put that in your report. My guess is there will be only a few fF variation over the frequency range of the kit. 
 
> In the datasheet of the calibration kit, it is mentioned that the standard definitions in table A-3 are for 8753 series; so 8753C is included. Moreover, and in order to install the kit into the NA, I use a software named “VNA Kit manager” that includes a big list of analyzers (including 8753A/B/C) and big number of calibration kits (85033D is also included). Nevertheless, the coefficients that you have mentioned are the same in this software. When I install the kit into the analyzer, 85033D calibration kit becomes the user kit and the VNA permits (by the softkeys) to choose the calibration method wanted. So I press the S11 1-port calibration (or full 2-port calibration) to perform the calibration using the coefficients of the 85033D kit.

I'd check what the data is in the 3.5 mm in your firmware. You might find the VNA directly supports the kit you have, in which case it is pointless uploading it as a user cal kit. Given you can only have one user kit in memory at any one time, it makes sence not to use that for a kit if is it in your firmware. 

You can check the offsets, C0, C1 etc of the kits defined in your firmware. If you try to modify the kit, you will see what the values are already present. Modifying the cal kit on the 8753 is certainly less than intuative. There is a point where it is tempting to use the soft keys to select the standard you want, but in fact you must use the up/down arrow keys. It is the same in my 8720D, but I wrote my own software to upload them anyway, since the Cal Kit manager is a windows program, and my VNA is currently connected to a workstation running Solaris, not Windows. 

My VNA has in its firmware the coefficients for the later 85033E kit so there would be no point me entering them for the 85033E, which I do happen to own. Given the 85033D is an older kit, and your universities 8753C is probably older than my 8720D, I would not be surprised if the data for the 85033D was already in the firmware of the 8753C. If it is, then that will allow you to keep the user kit for your own calibration kit. 

> > You too. It sounds an interesting project. If you don't mind, I'd appreciate you emailing me a copy of your final report once you have submitted it. I'd be interested to read it. 
> > 
> > Dr. David Kirkby  (david.kirkby@onetel.net)
> 
> I don’t have a problem, but I should rearrange this with my supervisor .

Yes sure. I suspect the copyright belongs to you anyway, but the last thing you want to do is upset your supervisor! 

Dave

你的困难有两个方面：1）你的微带线可能有损失，但你的短路或开路测量不应该包括损失。
这使得评估标准变得更加困难，但这可能不是您最大的问题;
2）你很可能在测试参考平面上存在不匹配，这将给你涟漪并使你的损失和相位由于重新反射而产生涟漪，这些反射并不是标准的真正部分。
您是否愿意发布一些情节：在删除多余的延迟之后，您是否可以发布每个短期，开放和短期和开放阶段的图表。
并张贴您的标准图片。
这样可以更容易地看出是否存在另一个悬而未决的问题。
如果在幅度上有涟漪，则必须是测量误差，因为短路必须具有全反射（折扣有点损失）。，同样对于开路。
这个确切的过程在我的书的第9章中有详细介绍，其中包含了使其工作的所有混乱和困难，关于这个主题的信息大约有20页：http：//www.wiley.com/WileyCDA/WileyTitle/productCd
-1119979552.html



     以下为原文

  You difficulty is two fold:

1) you likely have loss in your microstrip line, yet your measurment of the short or open  should not include the loss.  This makes estimating the standards more difficult, but it is likely not your biggest problem;

2) you very-likely have mismatch at the test reference plane, which will give you ripples and make your loss and phase have ripples due to re-reflections which are not really part of the standard.

Would you care to post a few plots:  Can you post a plot each of the magnitude of the short, and open, and phase of the short and open, after removing excess delay.  And post a picture of your standards.  It would make it much easier to see if there is another outstanding issue.

If there are ripples in the magnitude, it MUST be measurement error, as the short must have total reflection (discounting a little loss)., same for the open.

This exact process is detailed in Chapter 9 of my book, with all the messiness and difficulties in making it work, it's about 20 pages worth of information on just this subject: http://www.wiley.com/WileyCDA/WileyTitle/productCd-1119979552.html

> {quote：title = Dr_joel写道：} {quote}>为了获得最佳估计，您可能希望以更高的频率进行测量，并使用时域选通来消除输入连接器的影响。
Joel，大学拥有的8753C VNA，其中“频率爱好者”正在进行他的项目没有TDR选项。
正如您将在上面提到的那样，他曾尝试联系安捷伦销售部门，他们表示由于VNA已经过时，因此无法使用该选项。
看起来如果能找到某种方式让他获得选项010，那将是非常理想的。
你如何获得如此平滑的电容量？
当我尝试与你所做的非常相似时，但是使用85032B校准套件中的一个女性打开，我得到的是一个好的相位图，但看起来非常糟糕的电容图（见附件）。
使用相位计算电容：C = -tan（相/ 2）/（2 Pi f Zo）。
大约1 GHz以上的值看起来合理。
在6 GHz时，我测得大约121 fF，其中该标准的C0为119 fF，值看起来不错。
但是，如果电容是在较低频率下计算的，特别是在大约300 MHz以下，那么这些值就到处都是。
测量低频边缘电容有什么技巧吗？
你展示了一个非常好看的情节。
这只是PNA的高精度，还是你使用了一些特殊的技术？
戴夫



     以下为原文

  > {quote:title=Dr_joel wrote:}{quote}

> To get the best estimate, you might want to measure at much higher frequencies and use time domain gating to remove the effects of the input connector.

Joel, 

The 8753C VNA owned by the university where "Frequency Lover" is doing his project does not have the TDR option. As you will note above, he has tried contacting Agilent sales and they have said the option is not available since the VNA is obsolete. It seems like it would be really ideal if some way could be found for him to get option 010 added. 

How do you get such a smooth lot of capacitance as you show? When I try to do very similar to what you did, but using a female open from an 85032B cal kit, I get what looks like a good phase plot, but a really bad looking capacitance plot (see attached). Capacitance was computed from phase using:

C=-tan(phase/2)/(2 Pi f Zo). 

The values above about 1 GHz look reasonable. At 6 GHz I measure about 121 fF, which given C0 for that standard is 119 fF, the values look OK. But if the capacitance is computed at lower frequencies, especitaly below about 300 MHz, the values are all over the place. 

Is there any trick to measuring fringing capacitance at low frequencies? You show a very nice looking plot. Is that just the superior accuracy of the PNA, or is there some special technique you use? 

Dave

附件

• Massive-noise-on-computed-capacitance.PNG30.8 KB
  

> {quote：title = Dr_joel写道：} {quote}>看起来我们得到了垃圾邮件，也许温和会清除以前的邮件。
是的，该帐户用于发送大量一行消息，并带有指向其网站的链接。
我会报告我发现的那些。
>我没有测量那些结果，我只计算了模型的值。
哦，我原以为你在PNA上测量它们，而不是计算它们。
>当然，您会得到巨大的噪音，电容对相位迹线上的迹线噪声的灵敏度非常高。
无关紧要，反之亦然：相位对低频电容的微小变化的灵敏度很小。
这样做了。
>这就是为什么必须使用高频来产生电容值的原因。
如果它们在低频下完美无关紧要，因为它们对相位没有太大影响。
你让我觉得现在有点快乐！
戴夫



     以下为原文

  > {quote:title=Dr_joel wrote:}{quote}
> looks like we got spammed, maybe the moderate will clear the previous message.

Yep, 
that account is being used to send a lot of one line messages with a link to their site. I'll report those I find. 

> I didn't measure those results, I just computed the values of the model. 

Oh, I had assumed you measured them on a PNA, not computed them. 

> Of course you get tremendous noise, the sensitivity of capacitance to trace-noise on the phase trace is very high. Doesn't matter, the inverse is not true: the sensitivity of phase to small changes in capacitance at low frequency is tiny. 

That makes sence. 

> that is why you must use high frequencies to generate the capacitive values.  And it down't matter if they are perfect at low frequency, as they don't have much effect on the phase.

You make me feel a bit happier now! 

Dave

>>实际上，我并不相信并希望能够实现一个开放的标准响应，看起来像史密斯图表上的一个点。
首先，除非您的开路比测量的参考平面更短（偏移负偏），否则这是不可能的。
因为与教科书不同，ALL REAL开路传输线结构具有过多的边缘电容。
也许你误解了对开放式电路建模的想法：你正试图获得一个描述开路的模型，而不是试图创造一个理想的开放。
因此，PC板上的大多数开路电路具有小的，接近常数（±10％）的边缘电容。
我得到延迟正确，多余的电容将是50 fF + - 2 fF。
但是，如果你有一点延迟，那么C0项会受到很大影响。
模型中也存在“冗余”，也就是说，您可以使用两个具有不同项的模型来产生几乎相同的结果：一个可以具有更少的延迟和更多的C0，一个可以具有更多的延迟和更少的C0。
对于第一顺序，C0和延迟产生相同的相位响应变化。
最后，您看到的纹波仍然很可能是由于您使用SMA的响应而重新反射来自开放的信号。
我们的想法是在线的末端（应该具有几乎平坦的电容）对开路进行建模，而不是模拟SMA和开路的组合。
这就是为什么在试图确定真正的开放响应时，时间选通是如此重要。
由于SMA的错误导致的变化，您很可能“污染”您的开放模型，这不是开路的一部分。
校准后，如果您在打开的模型中不包含该错误，则会删除SMA中的错误;
但如果确实包含该错误，则在校准后，错误将保留在测量中，并且测量高反射负载（例如较长长度的短路传输线）将导致较差的结果。
注意：这些错误在三种情况下取​​消：那些与开路，短路和负载匹配的反射。
这就是为什么重新测量标准只能告诉您系统的稳定性（例如，您的电缆是否松动），但没有告诉您有关校准质量的任何信息。



     以下为原文

  > 
> Indeed, I’m not convinced and hope to achieve an open standard response that looks like a dot on the smith chart.

First, this is NOT possible unless your open circuit is shorter (offset negatively) than the reference plane of the measaurement.  Because unlike a text book, ALL REAL open circuit transmission line structions have excess fringing capacitance.  Maybe you mis-understand the idea of modeling the open cirucit:  You are trying to obtain a model that describes the open circuit, NOT trying to create an ideal open.

So, most open circuits on PC boards have small, nearl constant (+- 10%) fringing capacitance. I you get the delay correct, the excess capacitance will be something like 50 fF +- 2 fF.  BUT, if you have the delay off by a little, the C0 term is greatly affected.  There is also "redundancy" in the model, that is, you can have two models with different terms that produce practically identical results: one can have less delay and more C0, one can have more delay and less C0. To the first order, C0 and delay produce the same phase response change.

Finally, the ripple you are seeing is still most likely due to the response of the SMA you do use re-reflecting the signal from the open.  The idea is to model the open at the end of the line (which should have nearly flat capacitance), not to model the combination of the SMA and open.  That is why time gating is so important when trying to determine the true open response.  You have very likely "polluted" your open model with the variation caused by the error of the SMA, which is not part of the open circuit. 

After calibration, the error from the SMA is removed, if you don't include that error in your model of the open; but if you do include that error, then after calibration, the error will remain in the measurment and you will get poor results measuring highly reflective loads, such as a shorted transmission line of a longer length.  NOTE: these errors cancel in three cases: those reflections that match the open, short and load.  That is why remeasuring standards only tells you the stabiltiy of your system (are your cables loose, for example) but does not tell you anything about the qulaity of the calibration.

> {quote：title = Frequency Lover写道：} {quote}>开放标准的SMA连接器被替换为连接到短标准的连接器。
>>然后测量开放标准。
考虑了具有三个不同端口扩展（161,158和155ps延迟）的三次测量。
这样做是为了尽可能地实现单调相位响应。
我确信我完全确定你的“单调相位响应”是什么意思。
这不是我用过的术语。
我把它放在引号中，谷歌它，我只得到8次点击，这表明它不是我常用的术语。
但我认为您可能会以这种方式将端口扩展设置为不正确的值。
假设您的155,158和161 ps是相对于SMA连接器参考平面的端口扩展，我是否正确？
您是否尝试过计算偏移延迟应该是多少？
我可以想到两个延迟1）通过参考平面和微带线连接处的PTFE SMA连接器延迟。
2）延迟通过微带线，这取决于长度和有效介电常数。
Joel在一个线程（也许是这个）上说，对于同轴设备，偏移延迟是通过机械测量计算的，而不是电气测量计算的。
我想把这样的计算放在你的项目报告中会很好。
>好消息是，延伸后获得的边缘电容的曲线拟合产生的电容系数都在VNA接受的范围内（±10K）。这很大程度上是由于SMA连接器引起的不匹配。
作为示例，对应于161ps的端口扩展的系数如下：C0 = 103.89e-15F，C1 = -2427.94e-27F / Hz，C2 = -5286.42e-36F / Hz2＆amp;
C3 = 1088.79e-45F / Hz3。
Joel告诉你，边缘电容应该接近50 fF，所以这些对我来说都是错误的。
您大学系中是否有人可能使用带有TDR选项的VNA？
如果没有，并且您想要时域数据，我不介意为您免费测量它。
但是我在英国 - 我不知道你在哪里。
但小板上的邮资费用最低。请给david.kirkby发送电子邮件给我发送电子邮件>>>>如果你想完成，请发送电子邮件给onetel.net。
DaveEdited：drkirkby于2013年1月19日上午12:32



     以下为原文

  > {quote:title=Frequency Lover wrote:}{quote}
> The SMA connector of the open standard is replaced with that which was connected to the short standard.
> 
> The open standard is then measured. Three measurements with three different port extensions (161, 158, & 155 ps of delay) were considered. This is done in order to achieve a monotone phase response as much as possible. 

I'm sure entirely sure I know what you mean by "monotone phase response". It is not a term I have seen used. It I put it in quotation marks, and Google it, I only get 8 hits, which would suggest it is not a common term to me. But I think you might be setting your port extensions to an incorrect value this way. 

Am I right in assuming your 155, 158 and 161 ps are port extensions relative to the reference plane of the SMA connnector? 

Have you tried calculating an extimate of what the offset delay should be? There are two delays I can think of

1) Delay through the PTFE SMA connector between the reference plane and where it joins the microstrip.
2) Delay through the microstrip, which depends on the length and effective permittivity. 

Joel said on one thread (perhaps this one), that for coaxial devices, the offset delays are calculated by mechanical measurements, not electrical ones. 

I thnk putting such a calculation in your project report would be good. 

> The good news is that the capacitance coefficients resulting from curve fitting of the fringing capacitance obtained after extension are all in the range which is accepted by the VNA (±10K)  This is greatly due to the mismatch which was caused by the SMA connector. As an example, the coefficients corresponding to port extension of 161 ps are as follows: C0=103.89e-15 F, C1=-2427.94e-27 F/Hz, C2=-5286.42e-36 F/Hz2& C3=1088.79e-45 F/Hz3.

Joel has told you the fringing capacitance should be close to 50 fF, so these look wrong to me. 

Is there anyone in your university department that might have a VNA with a TDR option that you could use? If not, and you want the time-domain data, I don't mind measuring it for you free of charge. However I am in the UK - I have no idea where you are. But postage costs on a small board would be minimal Drop me an email to david.kirkby >>>> onetel.net if you want that done.

Dave

Edited by: drkirkby on Jan 19, 2013 12:32 AM

> {quote:title=drkirkby wrote:}{quote}
> 
> I thought I wrote a reply about 7 hours ago, so I'll try again:

I’m sorry for my late replies but this is because my time is not open for the project. I have other courses and the time of the project is limited. I appreciate your patience.

> 
> 1) I can't say I have come across the phrase "monotone phase response". Puttimg that in quotes into Google gives only 8 hits. Perhaps you could say exactly what you mean by this.

When I read in the papers of Agilent “…until the phase is monotonically negative”, I understood that the phase should be negative for the entire frequency band. But after the discussions in the forum, I realize now that “monotonically negative” means that the phase is always negatively decreasing; that is, no ripple (or even stable values) in the phase response despite that all phase values are below zero deg. Am I correct or not?
Let me add its meaning from WordWeb dictionary: “(mathematics) of a sequence or function; consistently increasing and never decreasing or consistently decreasing and never increasing in value”.

> 
> 2) I' can take a guess what you mean, but I'm not convinced it will lead you to the correct offset delay.

For this reason, I tried to take several values and perform several calibrations with different calibration kit definitions; but the problem always arises.
 
> 
> 3) Is this 155-168 ps a delay relative to the reference plane of the SMA connector? I'm guessing it is, but perhaps you can confirm.

The full 2-port calibration will fix the reference plane at the end of the connectors that are connected to the test cable; the port extension (155 – 161 ps) is then performed. That is, as you guess, the reference plane is relative to the reference plane of the SMA connector soldered to the board since it looks like the SMA connector of the 85033D calibration kit.
 
> 
> 4) Have you made an attempt to calculate from physical dimensions, an approximate value of the offset delay from the SMA reference plane? Such a calculation would be useful for your project report. If not, I'd suggest you try working it out, based on the delay through the SMA connector, the length of your microstrip lines, and the effective permittivity of your microstrip lines.

I think that you mean calculating the electrical length of the SMA connector and the microstrip line. But a question emerges; does such calculation exclude the effect of the transition and consequently its mismatch effect? And how could we calculate the capacitance if we just find the offset delay from the reference plane.
 
> 
> 5) If you can't get the TDR option added to the VNA in the university, have you tried asking others in your department if they have access to a VNA with the TDR option? Undergraduates tend to get given the old equipment, so you might find there are other VNAs around in your department which can do more. You might find there is someone with a PNA which will let you use it!

Unfortunately NO; no TDR option in my university because it doesn’t care much about microwave studies.
 
> 
> 6) If nobody else in your university is able to give you access to a VNA with the TDR option, then if you want, I don't mind giving you data from the time domain. Make another PCB, and solder the SMA, and ship it to me in the UK. There would be no charge for this - I'll even send it back at my cost, 
> 
> Although a university project is supposed to be your own work, in a case like this, if your university is lacking equipment that is quite critical to an experiment, it would normally be considered acceptable to get a device measured outside. You should ask your supervisor that, but I don't think that would be an issue, if I just gave you the time-domain data and you processed it. Drop me an email to david.kirkby@onetel.net if you want to do that and I'll give you address. 
> 
> I have here an 8720D VNA (50 MHz to 20 GHz) and an 85033E cal kit, which is specified for use to 9 GHz. It might work beyond a bit beyond 9 GHz, though I have no idea.

I really thank you for this and appreciate it a lot; but before doing this. Let me say that this would be the last solution because I find that this project is now a challenge and have to win it. Moreover, I think that we have to try more in order to get that option for my project and of course for other projects and students who come after my graduation. So I’ll keep what you suggested in mind :). 

> 
> Personally I would not put any faith in the calculations of C0, C1, C2 and C3 just because they are less than 10000 and so can be enterted as values in the VNA. You have an infinite number of wrong values which will fit, but all be wrong. Joel has already said what values you can expect, and this is outside that at most freqeuencies.

As I said to Joel, I’ll try to calibrate with only 50 fF fixed capacitance (only C0); I’ll post results as soon as possible.
 
> 
> > For the short standard, I used a new connector that gave a magnitude response of S11 very close to that obtained with theold connector.

> 
> Clearly something is wrong My guess is your offset delay is totally wrong. Mechanical measurements might help to clarify if you are in the right area. 
> 
> To me they do not look logical.

Hope that things go better.
 
> 
> Joel has already commented you are wrong in trying to do this, so there's no need for me to repeat that. 
> 
> Dave

嗨，> ..我的大学没有TDR选项，因为它不关心微波研究。
只需通过GPIB下载VNA跟踪数据，然后在PC上进行TDR数学运算。
完成后转换回时域并下载更新的数据并继续在VNA中进行分析。
或者继续在PC上进行分析。
在8753上，您可以在PC上按摩数据的自由度更高。除非您已经有一个，否则不需要使用$ K GPIB控制器。
有便宜的USB-to-GPIB产品可以直接从C / VB / Whatever代码控制，因此您可以轻松地来回传输数据。
当然，您需要学习GPIB命令并了解时域和频域之间的转换方式。
伊万



     以下为原文

  Hi,

>..no TDR option in my university because it doesn’t care much about microwave studies.

Just download the VNA trace data via GPIB and do you own TDR math on your PC. Once done convert back to time domain and download the updated data back and continue analyzing in the VNA. Or continue the analysis on the PC. You will have more freedom massaging data on the PC than on 8753. No need in a $K GPIB controller unless you have one already. There are inexpensive USB-to-GPIB products that can be controlled right from the C/VB/Whatever code so you can easily transfer data back and forth. Sure enough you'd need to learn GPIB commands and know how convertion between time and frequency domains. 


Ivan

> {quote：title = Miv写道：} {quote}>嗨，>>只需通过GPIB下载VNA跟踪数据，你就可以在PC上拥有TDR数学。
完成后转换回时域并下载更新的数据并继续在VNA中进行分析。
或者继续在PC上进行分析。
在8753上，您可以在PC上按摩数据的自由度更高。除非您已经有一个，否则不需要使用$ K GPIB控制器。
有便宜的USB-to-GPIB产品可以直接从C / VB / Whatever代码控制，因此您可以轻松地来回传输数据。
当然，您需要学习GPIB命令并了解时域和频域之间的转换方式。
>> Ivan Hi Ivan，我有一个USB-to-GPIB发射器，但是门控功能怎么样？
为了消除SMA连接器的影响，继续分析是必不可少的。
谢谢



     以下为原文

  > {quote:title=Miv wrote:}{quote}
> Hi,
> 
> Just download the VNA trace data via GPIB and do you own TDR math on your PC. Once done convert back to time domain and download the updated data back and continue analyzing in the VNA. Or continue the analysis on the PC. You will have more freedom massaging data on the PC than on 8753. No need in a $K GPIB controller unless you have one already. There are inexpensive USB-to-GPIB products that can be controlled right from the C/VB/Whatever code so you can easily transfer data back and forth. Sure enough you'd need to learn GPIB commands and know how convertion between time and frequency domains. 
> 
> 
> Ivan

Hi Ivan,

I do have a USB-to-GPIB transmitter, but what about the gating function? It is indispensable for continuing the analysis in order to remove the effects of the SMA connector.

Thanks

频率爱好者，我刚看了你在1月15日寄来的照片，我有几条评论： - 连接器似乎是durty，除非它是来自环境光/物体的阴影/反射产生了这种效果。
保持它们清洁很重要 - 尝试切断悬挂在PCB走线上的一对SMA腿。
它们可能导致连接器不匹配。
如果他们不这样做，你也不会因为删除它们而失去任何东西。



     以下为原文

  Frequency Lover,

I just viewed your pics that you sent on Jan 15 and I have a couple comments:

- the connectors seemed durty, unless it was shadows/reflections from the ambient light/objects that created that effect. It is important to keep them clean
- try cutting off the pair of SMA legs hanging over the PCB traces. Chances are they contribute to the connector mismatch. If they do not, you won't lose anything from removing them anyway.

>大学拥有的8753C VNA“频率爱好者”正在进行他的项目没有TDR选项。
正如您将在上面提到的那样，他曾尝试联系安捷伦销售部门，他们表示由于VNA已经过时，因此无法使用该选项。
看起来如果能找到某种方式让他获得选项010，那将是非常理想的。
>最后发现，对于8753C，您肯定没有足够的分辨率来解决打开的SMA连接器。
通过电路板的外观，开口距离SMA连接器约3-5厘米。
即使在PCB材料中，这也可能是200-400 psec的往返延迟。
如果是6 GHz，8753C的门控分辨率大约为300 psec，如果是3 GHz则大约为600 psec。
您需要大约100 psec的分辨率才能成功，或者需要大约20 GHz的频率范围。
抱歉。
重力糟透了。



     以下为原文

  > The 8753C VNA owned by the university where "Frequency Lover" is doing his project does not have the TDR option. As you will note above, he has tried contacting Agilent sales and they have said the option is not available since the VNA is obsolete. It seems like it would be really ideal if some way could be found for him to get option 010 added. 
> 
It finally occured to me that with 8753C, you will surely NOT have sufficient resolution to resolve the SMA connector from the open.  By the looks of the board, the open is about 3-5 cm from the SMA connector.  Even in PCB material, this will be a round trip delay of maybe 200-400 psec.  The gating resolution of the 8753C is on the order of 300 psec if it is 6 GHz, and 600 psec if it is 3 GHz.  You need a resolution on the order of 100 psec to be successful, or a frequency range on the order of 20 GHz.  Sorry.  Gravity Sucks.

> {quote:title=Frequency Lover wrote:}{quote}
> > {quote:title=Dr_joel wrote:}{quote}
> > It finally occured to me that with 8753C, you will surely NOT have sufficient resolution to resolve the SMA connector from the open.  By the looks of the board, the open is about 3-5 cm from the SMA connector.  Even in PCB material, this will be a round trip delay of maybe 200-400 psec.  The gating resolution of the 8753C is on the order of 300 psec if it is 6 GHz, and 600 psec if it is 3 GHz.  You need a resolution on the order of 100 psec to be successful, or a frequency range on the order of 20 GHz.  Sorry.  Gravity Sucks.
> Actually, the length of the microstrip line is 2 cm and the delay corresponding to the microstrip + the SMA connector is of the order of 165 ps. Thus less than 200ps.

> Even if this delay is big, I can minimize the length of the MS line to 1 cm (or even 0.8 cm).

Frequency Lover , 
the insufficient resolution Joel mentions will not be solved by making the microstrip shorter - that would make the problem worst! You would need to either reduce the resolution, which needs a VNA working to a higher frequency, or increase the distance between the two reflections. 

There is undoubtedly a lot more information about this in Joel's book, but here are a few equations taken from the manual for my 8720D VNA. There's a fair bit of interfmation on this is the 8720D user's manual, so you might want to look at that, though I suspect an application note would be better. 

First there is a maximum distance which can be used without alaising:That's not important to you, but I'll put it anyway. 

*Measurement range* = 

1/(delta f)
where delta f is the spacing between frequency data points. 
measurement rage = (number of points -1)/delta f

There's an example of using a frequency range of 2 MHz to 2.001 GHz, using 201 points, which works out to 30 m. 
(Worth checking yourself)

But the more important issue to you is the time domain resolution. If that is too long, then you will not be able to resolve the difference between the reflection from the open circuit and the reflection from the SMA connector. Anyway, to quote from the HP 8720D manual:

*Response resolution*
Time domain response resolution is defined as the ability to resolve two closely spaced responses, or a measure of how close two responses can be to each other and still be distinguished from each other. For responses of equal amplitude, the response resolution is equal to the 50% (-6 dB) impulse width. It is inversely proportional to the measurement frequency span and is also a function of the windows used in the transform. ...

50% calculated impulse width = 0.98 * 2 / f, where the width is in ns and the frequency in GHz.

For example, using the formula for the bandpass mode with a normal windowning function  for a 50 MHz to 13.05 GHz measurement (13 GHz span):

50% calculated impulse width = 0.98*2/13 = 0.151 ns
Electrical length (in air) = t * c
= 45.3 mm

You obviously need to get below the 50% point to distinguish two reflections. I expect in your case, you need to be significantly below the 50% point, as the reflection from the open is close to 100%, and that from the SMA is close to 0%. 

*If* you could get the TDR option added, *and* the PCB was much longer, you *might* manage this. But obviously the loss would increase too, which might present its own problems. 

I offered to try to help with my VNA for you, as that does have the TDR option. But although my HP 8720D VNA works to 20 GHz, my Agilent 85033E cal kit is specified to a maximum frequency of 9 GHz, so I think I'd be out of luck too. I guess there's  a resonable chance my cal kit might work OK at 10 GHz, but I've no idea if it could be used at 20 GHz at reduced accuracy. I suspect the polynomial fit would be poor, but one might get away with assuming a constant value of C0, and setting other coefficients to 0. But it's hard to know.

Joel has told you the fringing capacitance will be about 50 fF. It might be worth trying to find a peer-revieweed reference to this, and then just use 50 fF in your report, saying it is impossible with the hardware you have to do any better. So set C0 = 50, C1=C2=C3=0. As someone who has supervised a number of B.Sc and M.Sc projects, I would normally discourage references to web sites, and want peer reviewed journals, but at a push, a reference to an Agilent web site, but an acknowledge expert in this field, it would be OK. You could back up Joel's knowledge with a reference to his book. 

Sometimes you just have to accept you can't do what you would like to do due to limitations of your equipment. This might be one of those instances. You could try a new thread, wth a title something like +"Is there anyone with a 20+ GHz VNA with TDR option willing to help a student?"+  Personally I'd look at trying to seek help from someone with better hardware. If nothing else, it would show you have tried the best you can, and that can only be to your advantage. 

BTW, for what it is worth,  when I worked at Marconi Optical Components, I supervised an M.Sc student from Essex University. He won an award for his project from Agilent. I'm not sure how Agilent got involved though - perhaps it was some connection between Agilent and the University of Essex. Other than spending a small fortune with Agilent on optical test equipment, I had no involvement. 

Dave

Edited by: drkirkby on Jan 23, 2013 2:12 PM

> {quote：title = Dr_joel写道：} {quote}>你可以使用“长线”短路来帮助你模拟开路。
>>您会发现将短延迟设置为零，但这会使参考平面处于短路状态。
我会测量通孔的长度，并通过有效延迟来延迟延迟。
>过孔浸没在电介质中，看起来像带状线。
因此，我应该找到具有通孔物理长度的带状线的电气长度。
你是否同意我的观点？
>在较长的线上使用短路（在最高频率下可能有2或4个波长）。
校准后测量。
它应该表现出一些单调的损失。
如果它显示涟漪，则表示您在打开或加载时出错。
我会先设置C0并打开延迟。
如果必须，可以设置C1。
您可能永远不会需要C2或C3。
猜测一些值，校准，测量偏移短路并注意纹波。
>“校准后测量。”您的意思是使用85033D校准套件进行校准吗？
如果是，开放或加载的问题是什么？
如果否，如果尚未定义电容系数，我该如何校准？
我是否从导纳图中取出C0系数并猜测C1？
“你可能永远不会需要C2或C3。”我知道最高频率是6 GHz，我可以丢弃C2和C3。
C3？
所有注释和论文都指出，在这样的频率下，这些系数对于完成校准是必不可少的。
>然后猜一个更大的值（可能大20％），并重新校准并注意波纹。
如果纹波改善，继续朝这个方向前进，如果情况变得更糟，则转到更低的值。
>>我们知道偏移短路（只是较长的微带线上的通路）应该只是一个平滑的略微有损回波损耗，因此如果它有波纹，则表示校准问题。
>我该如何解决这个问题？
在VNA中是否有任何内部测试以确保它不是机器的问题，而是人类的问题？
>但是，你会在我的书的第9章中看到这一点，你最大的问题可能是你正在使用的SMA到PC板连接器的质量不一致。
如果您用于打开的那些与短路或负载不匹配，那么您就是SOL。
没有什么可以做，但得到更好的连接器。
我正在使用PCB安装垂直插孔SMA连接器（但水平焊接到电路板上），是否不一致？
4种标准（SOLT）的所有连接器都是新的，并且是相同类型的并且来自同一制造商。
还有什么可做的吗？
感谢您的回应乔尔博士。



     以下为原文

  > {quote:title=Dr_joel wrote:}{quote}
> you can use a "long-line" short to help you model the open circuit.
> 
> you are find to set the short delay to zero, but that makes the reference plane at part-way through the short.  I'd measure the length of the via and back off the delay by that effective delay.
> 

The vias are immersed in the dielectric, it looks like a stripline. Thus, I should find the electrical length of a stripline having the physical length of the vias. Do you agree with me?

> Use a short on a line that is longer (maybe 2 or 4 wavelengths at your highest frequency). Measure it after calibration.  It should show some monotonic loss.  If it shows ripples, you have errors in your open or load.  I would start with setting only C0 and open delay.  If you must, you can set a C1.  You will likely never need C2 or C3.  Guess some values, calibrate, measure the offset short and note the ripple.
> 

“Measure it after calibration.” Do you mean the calibration using the 85033D calibration kit? If yes, what will be the problem of open or load? And if No, how can I calibrate if the capacitance coefficients are not defined yet? Do I take the C0 coefficient from the admittance chart and make a guess for C1?
“You will likely never need C2 or C3.” Knowing that the maximum frequency is 6 GHz, can I discard C2 & C3? All notes and papers state that at such frequency, these coefficients are indispensible for completing the calibration.

> Then guess a bigger value (maybe 20% bigger), and recalibration and note the ripple.  If the ripple improves, keep going in that direction, if it gets worse, go to a lower value.
> 
> We know the offset short ( just a via on a longer micrstrip line) should be just a smooth slightly lossy return loss, so if it has ripples, it indicates a calibration problem.
> 

How can I solve this problem? Is there any internal test in the VNA to be sure that it is not the problem of the machine, but a human one?

> BUT, and you'll see this in chapter 9 of my book, your biggest problem is likely inconsistent quality of the SMA to PC board connectors you are using.  And if the ones you are using for the open don't match the short or the load, you are SOL.  Nothing you can do but get better connectors.

I am using a PCB mount vertical jack SMA connector (but soldered horizontally to the board), is it inconsistent? All connectors for the 4 standards (SOLT) are new, and of the same type and from the same manufacturer. Is there anything else to do?
Thanks for your response Dr Joel.

我已经绘制了你未尝试进入VNA的系数。
我认为总体情节存在很大问题。
它显示电容首先下降很多，然后增加。
当然，我见过的任何同轴线，边缘电容随频率增加而不会下降。
增量只有几个fF。
这告诉我你的系数严重错误。
恕我直言，你需要按照你的标准延迟补偿。
不要问我这样做，因为我遇到了同样的问题。
虽然我是同轴的。
戴夫



     以下为原文

  I've plotted the coefficients you are unsucessfully trying to enter in your VNA. I think there's a big problem with the overall plot. It shows the capacitance first decreasing quite a bit, then increasing. Certainly any coaxial line I have seen, the fringing capacitance increases with frequency, and does not drop. The increses is only a few fF. 

This suggests to me your coefficents are seriously wrong.

IMHO, you need to work at the delay offsets to your standards. Don't ask me to do it, as I'm having much the same issue,. although mine is coaxial. 

Dave

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我想这意味着Copper Mountain在生产便宜的（600美元）1.5 GHz“N”校准套件http://www.coppermountaintech.com/products/6/N1.1/而不需要男性扩展器方面稍微合理一些
通过负偏移延迟（-13.68 ps）补偿男性延伸的缺失。
但是从85032B手册中复制了C0，C1，C2和C3系数！
为了公平对待他们，他们制造廉价（ish）校准套件的论点是，他们不能卖出3000美元的VNA，并期望客户再为支付套件支付相同费用。
他们的MD表示他们不想与Maury Microwave，Spinner，Rosenberger等竞争。但Copper Mountain的C0，C1，C2和C3系数都只是HP 85032B手册的副本，但是小数点后1位，
我很开心，因为很明显，如果男性扩展器不存在，边缘电容会发生相当大的变化。
我想拥有所有这些数字看起来很不错，即使它们是从HP / Agilent产品中复制的！
有时简单的事情让我很开心！
Dave编辑：drkirkby于2013年1月16日9:21 AM编辑：drkirkby于2013年1月16日上午9:34



     以下为原文

  I guess this means Copper Mountain are slightly more justified in producing a cheap ($600) 1.5 GHz 'N' cal kit 

http://www.coppermountaintech.com/products/6/N1.1/

without an extender for the male, then compensating for the lack of male extension by a negative offset delay (-13.68 ps). BUT the C0, C1, C2  and C3 coefficients are copied from the 85032B manual! To be fair to them, their argument for producing a cheap(ish) cal kit is they can't sell a $3000 VNA and expect customers to pay the same again for a cal kit. Their MD said they have no desire to compete with Maury Microwave, Spinner, Rosenberger etc. 

But the fact Copper Mountain's C0, C1, C2 and C3 coefficients are all just copies from the HP 85032B manual, but rounded by 1 less decimal place, did amuse me somwhat, given it is clear the fringing capacitance is going to change quite a bit if the male extender is not present. I guess it looks good to have all these numbers, even though they are copied from an HP/Agilent product!

Sometimes simple things amuse me! 

Dave

Edited by: drkirkby on Jan 16, 2013 9:21 AM

Edited by: drkirkby on Jan 16, 2013 9:34 AM

> {quote：title = drkirkby写道：} {quote}>我不确定报告这个的最佳位置，但是这个论坛的消息正在丢失。
首先他们出现，然后他们去，然后几个小时后他们再次出现。
>> Dave你能把你的回复作为私信发送吗？
如果您没有看到我对您的问题的最后回复，我也会将其作为私人消息发送给您。



     以下为原文

  > {quote:title=drkirkby wrote:}{quote}
> I'm not sure the best place to report this, but messages are getting lost from this forum. First they appear, then they go, then they reappear some hours later. 
> 
> Dave

Can you please send your reply as a private message?
If you didn't see my last reply to your questions, I'll also send them as a private message.

重复和帖子的道歉在过去几天消失并再次出现 - 支持人员向我保证问题现在已经解决，但他们仍在继续监控。



     以下为原文

  Apologies for the duplicates and posts disappearing and reappearing over the last few days - the support guys assure me that the problem is now resolved but they are continuing to monitor.