如何生成占空比为50％的pwm信号

HeloIIM尝试用PIC32 MZ2048 EFH100生成占空比为50%的PWM信号，这是我的代码，对于头文件[/Fix]，IFNDEF SPIPWMH H/*防止多个包含*/y*定义SPIPWMYH//C’源代码配置语句//DEVCFG3//USERID＝不设置HeNETRMII/MII启用（RMII使能）Apple TracMa配置FETHOI= ON/Ethernet I/O PIN选择（默认以太网I/O）α-PracMA配置PGL1WORE = / /允许组锁定单向配置（仅允许一个重新配置）* PrimaMac配置PMDL1WORE = / /外围模块禁用配置（允许）仅一个重新配置）（PLL Input Divider）PraceMac配置IOL1WOR/ONEXT PIN选择配置（仅允许一个重新配置）α-PracMA配置FuBidio= ON//USB UBID选择（由USB模块控制）//DEVCFG2* PrimaMatg配置FPLLIDEV＝DIVIO1//系统（2x除法器）FFG LFLLRNG＝RangeE551010MHZ／系统PLL输入范围（5-10MHz输入）μ-PracMA配置FPLILKK＝PLLY-FRC//系统PLL输入时钟选择（FRC输入到系统PLL）α-PrAPMA配置FPLLMult＝Mulr50//PLL乘法器（PLL乘50）tput Clock Divider（2x除法器）α-PrimaMac配置，LoFLQ24MH//USB PLL输入频率选择（USB PLL输入为24 MHz）//DVCFG1α-PrAPMA配置FFONC＝PLSL/ /振荡器选择位（系统PLL）α-PrimaMatg配置DMtinv= WiNe127Al128//DMT计数窗口间隔（窗口/间隔值I）S 127/128计数器值（Ox PracMA配置）FSOSCEN＝OF//次级振荡器使能（禁用SOSC）α-PrimaAcOfIOS= OF//内部/外部切换（禁用）α-PracMA配置POSCMOD＝EC//主振荡器配置（初级OSC禁用）α-PracMA配置OSCIOFNC＝OF//CLKO输出S在OSCO PIN（禁用）中，IGOC（Timer Postscaler）的PraceMac配置，FCKSM＝CSEMME//时钟切换和监视器选择（启用时钟开关，启用FSCM）α-PrAPMA CONFIG WDTPS＝PS1048 57 6/ /看门狗（1∶1048 57）DT在Flash编程过程中停止运行，{ Trac-PracMaMig.CONFIG =正常/ /看门狗定时器窗口模式（看门狗定时器是在非窗口模式）中，Trac-MaqMa配置FFDTEN= OF//看门狗定时器启用（WDT禁用）α-PrAPMA配置FWDTWISZZ＝WiSZZ25//看门狗定时器窗口大小（窗口大小为25%）G DMTCNT＝DMT31／/死人定时器计数选择（2 ^ 31（2147483648））*GMA配置ICSIL＝ICSU-PGX2//ICE/ICD COMM信道选择（通信在PGEC2/PGED2）上。KE//动态Flash ECC配置（ECC和动态ECC被禁用（ECCCON位可写）），γ-PracMaMig-COFIG FSHIL= OF//FLASH睡眠模式（当设备处于休眠模式时Flash被关闭）* PrimaMac配置= dggPul//Debug模式CPU访问权限（允许CPU访问所有的CPU）任务区域）SyPrimaMac配置，SMCLR＝MCLRYNORM//软主清除允许位（MCLR引脚产生正常系统复位）α-PracMA配置SFOSGRAMP＝GAAIN 2X//次级振荡器增益控制位（2X增益设置）α-PrAPMA配置SCOSBOOST＝ON / /次振荡器Boost启动启动位提高振荡器的开机启动）（γ）PrimaMatg配置，POCSGROW＝GAAIN 2X//主振荡器增益控制位（2X增益设置）α-PrAPMA配置POSBOOST＝ON /主振荡器Boost启动启动位（提高振荡器的开机启动）Oracle EJTAG功能性//DEVCP0X-PARMARMA配置CP=关闭/ /代码保护（/SED3//DEQADC0//DEVADC1//DEVADC2//DEVADC3//DEVADC4//DEVADC7//OXY）PracMA配置语句应该在Project文件之前包含.//使用Project EnMUX代替ON定义ON和OFF。h & gt；//5ls- l复制粘贴，α-IFDEF，CpulsPullSuthn“C”{0—172MV，有时我得到正确的形状，我不确定如果主代码不正确，或者是随机行为的头文件，谢谢你的时间。



      以下为原文

    hello

im trying to generate a pwm signal  with duty cycle 50% with the pic32MZ2048EFH100
here is my code,



OC1CON = 0x0000; // Turn off the OC1 when performing the setup
T2CON=0x0;
OC1R = (uint16)(PR_2+1)/2; // Initialize primary Compare register
OC1RS = OC1R; // Initialize secondary Compare register
OC1CON = 0x0006; // Configure for PWM mode without Fault pin enabled, timer2, 16bit comparaison, SIDL continue in idle mode
PR2 = PR_2; // desired periode
TMR2=0;
IFS0CLR = 0x00000100; // Clear the T2 interrupt flag
IEC0CLR = 0x00000100; // disable T2 interrupt
//IPC2SET = 0x0000001C; // Set T2 interrupt priority to 7
IEC0bits.OC1IE=0;//disable output compare interrupt
T2CONSET = 0x8000; // Enable Timer2 PBCLK3=100MHZ , prescale 1:1
OC1CONSET = 0x8000; // Enable OC1


for the header file
[/code]
#ifndef SPIPWM_H /* Guard against multiple inclusion */
#define SPIPWM_H
// 'C' source line config statements
// DEVCFG3
// USERID = No Setting
#pragma config FMIIEN = OFF // Ethernet RMII/MII Enable (RMII Enabled)
#pragma config FETHIO = ON // Ethernet I/O Pin Select (Default Ethernet I/O)
#pragma config PGL1WAY = ON // Permission Group Lock One Way Configuration (Allow only one reconfiguration)
#pragma config PMDL1WAY = ON // Peripheral Module Disable Configuration (Allow only one reconfiguration)
#pragma config IOL1WAY = ON // Peripheral Pin Select Configuration (Allow only one reconfiguration)
#pragma config FUSBIDIO = ON // USB USBID Selection (Controlled by the USB Module)
// DEVCFG2
#pragma config FPLLIDIV = DIV_1 // System PLL Input Divider (2x Divider)
#pragma config FPLLRNG = RANGE_5_10_MHZ // System PLL Input Range (5-10 MHz Input)
#pragma config FPLLICLK = PLL_FRC // System PLL Input Clock Selection (FRC is input to the System PLL)
#pragma config FPLLMULT = MUL_50 // System PLL Multiplier (PLL Multiply by 50)
#pragma config FPLLODIV = DIV_2 // System PLL Output Clock Divider (2x Divider)
#pragma config UPLLFSEL = FREQ_24MHZ // USB PLL Input Frequency Selection (USB PLL input is 24 MHz)
// DEVCFG1
#pragma config FNOSC = SPLL // Oscillator Selection Bits (System PLL)
#pragma config DMTINTV = WIN_127_128 // DMT Count Window Interval (Window/Interval value is 127/128 counter value)
#pragma config FSOSCEN = OFF // Secondary Oscillator Enable (Disable SOSC)
#pragma config IESO = OFF // Internal/External Switch Over (Disabled)
#pragma config POSCMOD = EC // Primary Oscillator Configuration (Primary osc disabled)
#pragma config OSCIOFNC = OFF // CLKO Output Signal Active on the OSCO Pin (Disabled)
#pragma config FCKSM = CSECME // Clock Switching and Monitor Selection (Clock Switch Enabled, FSCM Enabled)
#pragma config WDTPS = PS1048576 // Watchdog Timer Postscaler (1:1048576)
#pragma config WDTSPGM = STOP // Watchdog Timer Stop During Flash Programming (WDT stops during Flash programming)
#pragma config WINDIS = NORMAL // Watchdog Timer Window Mode (Watchdog Timer is in non-Window mode)
#pragma config FWDTEN = OFF // Watchdog Timer Enable (WDT Disabled)
#pragma config FWDTWINSZ = WINSZ_25 // Watchdog Timer Window Size (Window size is 25%)
#pragma config DMTCNT = DMT31 // Deadman Timer Count Selection (2^31 (2147483648))
#pragma config FDMTEN = OFF // Deadman Timer Enable (Deadman Timer is disabled)
// DEVCFG0
#pragma config DEBUG = OFF // Background Debugger Enable (Debugger is disabled)
#pragma config JTAGEN = OFF // JTAG Enable (JTAG Disabled)
#pragma config ICESEL = ICS_PGx2 // ICE/ICD Comm Channel Select (Communicate on PGEC2/PGED2)
#pragma config TRCEN = OFF // Trace Enable (Trace features in the CPU are disabled)
#pragma config BOOTISA = MIPS32 // Boot ISA Selection (Boot code and Exception code is MIPS32)
#pragma config FECCCON = OFF_UNLOCKED // Dynamic Flash ECC Configuration (ECC and Dynamic ECC are disabled (ECCCON bits are writable))
#pragma config FSLEEP = OFF // Flash Sleep Mode (Flash is powered down when the device is in Sleep mode)
#pragma config DBGPER = PG_ALL // Debug Mode CPU Access Permission (Allow CPU access to all permission regions)
#pragma config SMCLR = MCLR_NORM // Soft Master Clear Enable bit (MCLR pin generates a normal system Reset)
#pragma config SOSCGAIN = GAIN_2X // Secondary Oscillator Gain Control bits (2x gain setting)
#pragma config SOSCBOOST = ON // Secondary Oscillator Boost Kick Start Enable bit (Boost the kick start of the oscillator)
#pragma config POSCGAIN = GAIN_2X // Primary Oscillator Gain Control bits (2x gain setting)
#pragma config POSCBOOST = ON // Primary Oscillator Boost Kick Start Enable bit (Boost the kick start of the oscillator)
#pragma config EJTAGBEN = NORMAL // EJTAG Boot (Normal EJTAG functionality)
// DEVCP0
#pragma config CP = OFF // Code Protect (Protection Disabled)
// SEQ3
// DEVADC0
// DEVADC1
// DEVADC2
// DEVADC3
// DEVADC4
// DEVADC7
// #pragma config statements should precede project file includes.
// Use project enums instead of #define for ON and OFF.
#include

//5lss lcopy paste
#ifdef __cplusplus
extern "C" {
#endif

#ifdef __cplusplus
}
#endif
#endif /* _EXAMPLE_FILE_NAME_H */
/* *****************************************************************************
End of File
*/
[/code]

sometimes im reading the low value from the oscilloscope a negative value instead of zero -172mv
and sometimes i obtain a correct shape im not sure if the code in the main is incorrect or is it the header file with random behavior

thank you for your time

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