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在DSSPICEV处理器上的通用硬陷阱的原因是什么?一个简短的解释应用程序和我们遇到的问题:DSPIC32 EV32 GM00 4在工业环境中用于测量NTC远离主控制器的温度。DSPIC被用作一个串行(LIN)接口的奴隶,在大约5米的距离。未受管制的9V电源(VBAT为LIN接口)也通过该电缆提供,并在本地用于DSPIC。另一个DSPIC串行通道用于调试目的,通常不连接。在测试台上,处理器几乎按预期操作。然而,每天几次,处理器重置自身。调试表明,这源自于接收“通用硬陷阱”。一旦调试器(ICD3)被连接,就没有接收到更多的硬陷阱。当在实际环境中使用时,硬陷阱的数量要高得多,每分钟几次,以至于无法正常操作。在这里连接调试器也可以防止硬陷阱发生。用一个将MCLR线路短路到+5V电源的报头替换调试器与连接调试器是不一样的。我们已经使用一个8位PIC处理器从一个早期的项目中复制了部分示意图,它已经运行了好几年了,没有任何问题。现在我们已经尝试了几种可能的解决方案,增加了额外的解耦,增加了调试连接器的额外的上拉,但是没有这种工作。因此,这将有助于了解硬陷阱的可能原因。DSPIC的数据表提到了双配合闪存错误作为可能的原因,但没有检测到单个单位闪存错误(可以通过启用中断ECSBEE来计数)。是否有可能只有双位错误和根本没有一个比特错误?这对我来说似乎不合乎逻辑。
以上来自于百度翻译 以下为原文 What is the cause of the generic hard trap on the dsPIC32EV processor? A short explanation of the application and the problems we encounter: The dsPIC32EV32GM004 is used in an industrial environment for measuring the temperature of NTC's remote from the main controller. The dsPIC is used as a slave over a serial (LIN) interface, at about 5 meters distance. Un unregulated 9V power supply (Vbat for the LIN interface) is also supplied by means of this cable and used locally for the dsPIC. Another dsPIC serial channel is used for debug purposes and normally not connected. On the test-bench the processor operates nearly as expected. However a few time a day, the processor resets itself. Debugging has showed that this originates from receiving a "generic hard trap". Once the debugger (ICD3) is connected, no more hard traps have been received. When used in the real environment, the number of hard traps is much higher, several each minute, so much that no normal operation is possible. Connecting a debugger here also prevents the hard trap from occurring. Replacing the debugger with a header shorting the MCLR line to the +5V power supply was not the same as connecting the debugger. We have copied part of the schematics from an earlier project using a 8 bit PIC processor, which has been running for several years now without any problem. We have now tried several possible solutions
Therefor it would help to know the possible causes of the hard trap. The datasheet of the dsPIC mentions double fit flash errors as a possible cause, but not a single single bit flash error has been detected (can be counted by enabling interrupt ECCSBEIE). Is it possible to have only double bit errors and no single bit errors at all? That doesn't seem logical to me. Attached Image(s) |
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4个回答
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这个陷阱通常是由ECC双位错误引起的。陷阱的默认中断处理程序只会导致重置。有一些微芯片的例子来说明当陷阱发生时,什么代码行正在执行。您也可以在论坛中搜索“WasWASI”,也可以查看ErrasaTHT。TP://WW1.MICCHIP.COM/DeLoSt/En/DeVICECD/O9000619K.PDFECECCDBE位总是被读取为“0”,并签出“24”。
以上来自于百度翻译 以下为原文 This trap is generally caused by a ECC double-bit error. The default interrupt handler for a trap just causes a reset. There are some Microchip examples of how to find out what what line of code was executing when the trap occured. you can also search the forum for "wherewasi" also look at the errata http://ww1.microchip.com/downloads/en/DeviceDoc/80000619k.pdf The ECCDBE bit is always read as ‘0’ and check out #24 |
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你的时钟频率是多少?你有没有冒险去看一眼这些错误?最后,你会两眼都感到悲伤:-请不要抱怨。在使用MCU时,经常会出现一些螺母和螺栓,这会使生活变得辛辣。
以上来自于百度翻译 以下为原文 What is your clock frequency ? And did you ever bother to risk an eye reading the erratas ? Eventually you'd risk both eyes sad: And - please - do not complain. There are always some nut and bolts to be expected when using MCUs from M...chip. This makes life spicy... |
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@博斯科已经安装了自己的陷阱处理程序,用于调试目的,应该在串行调试端口上显示程序计数器。对于数学错误(可以很容易地生成),这很好。我也读了勘误表文件,并得出结论,24是不适用的,因为我这里的硅修订版是A7,勘误表只适用于A4。然而,它可能会使处理器速度降低到40 MHz,以防万一。我确实错过了36(ECCDBE位未设置):从来没有发生过一个比特错误,为什么应该是双位错误?DU900010000我会尝试降低时钟速度,因为它可能会有帮助。我一直在使用微芯片组件足够长(近20年我认为)在使用组件之前读取ErATA,并且仍然可以预料到“惊喜”,因为勘误表只包含确认的问题,而不是那些问题。“正在调查中”。然而,我从未见过测试台性能和真实世界性能之间的差别。在所有其他情况下,微芯片组件的性能稳定,不易受环境影响。由于连接ICD3时问题已经解决,因此,通过将ICD2附加到调试连接器上,可以立即解决问题。我有几个ICD2还在这里,现在可以使用了。眨眼:
以上来自于百度翻译 以下为原文 @bosco I already installed my own trap handlers for debugging purposes, which should display the program counter on the serial debug port. For the math error (that can be easily generated) this works fine. I also read the errata file, and concluded that #24 was not applicable, because the silicon revision I have here is A7 and the errata only applies to A4. Nevertheless, it might make sence to reduce the processor speed to 40 MHz, just in case. I had indeed missed #36 (ECCDBE bit not set): no single bit errors ever occured, why should be be double bit errors? @du0000001 I'll try reducing the clock speed, since it might help. I've been working with microchip components long enough (nearly 20 years I think) to read the erata before using the components, and still 'surprises' can be expected, since the errata only contains the confirmed issues, not the ones 'under investigation'. However, I've never seen this difference between test-bench performance and real world performance. In all other cases, the microchip components behaved stable, not easily influenced by the environment. Since the problem was gone when connecting a ICD3, the problem might be solved for the moment by attaching a ICD2 to the debug connector. I've got a couple of ICD2's still laying around here, now the can be used. wink: |
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如果它没有在工作台上工作——你希望在生产环境中怎么样?在“现实世界”的情况下,事情可能会变得更加复杂:中断的时间不太规则和可重复性,供应嘈杂等等。原来的帖子看起来像你有一些问题“在工作台上很少见到”,“在生产环境中永久地看到”。我最初开始用AHIT来检查AL。供应包括VCAP。VCAP上的电容器。特别是ESR值,以确保bean计数器不随帽的规格。我放弃了当发现在勘误表中的问题。但这可能是一个好主意,因为ICD3通常有助于电力供应-最终改善一些关键的情况。所以现在…
以上来自于百度翻译 以下为原文 If it ain't work on the bench - what do you expect in the production environment ? Under "real world" conditions, things may become more complicated: interrupt timing less regular and repeatable, supply noisier etc. The original post looked like you have some issue "rarely seen on the bench", "permanently seen in the production environment". I originally started with a hint to check ALL supplies - including Vcap. And the capacitor at Vcap. Especially the ESR value to make sure that the bean counters did not twiddle with the cap's spec. I discarded that when finding the issues in the errata. But maybe it would be a good idea as the ICD3 usually contributes to the power supply - eventually improving some critical situation. So now ... |
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