PIC24FJ128GB202内部RTCC没有时间

我使用PIC24FJ128GB202作为USB数据记录器应用程序。我已经连接了3V3VBAT。3V3VBAT还为3TC76KHz的晶体供电，为RTCC（通过二极管）的SOSC。当电路板在正常庄园中被完全供电时，时钟功能良好。当电源被移除时，晶体是。然而，仍然振荡（我已经用OSSCLILCOPE检查了这个），时钟没有继续在RTCC中进展。VBAT的电压是3.2V。当电源返回到PCB时，RTCC从主电源被从板上移除的时间继续，而不是现在的时间。读取数据表，我不需要配置任何东西，以使RTCC在使用SOSC时保持时间。我也找不到标记RTCBAT来检查这是被设置的（数据表称这应该默认设置为1）以确保VTBT启用RTCC操作。下面是我的配置代码和时钟配置从安装例程。有什么建议，我做错了什么？我肯定这很简单！如果我使用LPRC作为时钟源代替SOSC，时钟工作完美。我发现LPCR时钟源在24小时内获得或丢失了一个小时，所以我很想切换到SOSC。



      以下为原文

    I am using the PIC24FJ128GB202 for a USB datalogger application.

I have connected a 3V3 VBAT.

The 3V3 VBAT also powers a 32.768KHZ crystal for the SOSC for the RTCC (through a diode).

The clock functions fine when the board is fully powered up in the normal manor.

When power is removed, the crystal is still oscillating (I have checked this with an osscillocscope), however, the clock does not continue to progress in the RTCC. The voltage of VBAT is 3.2V.

When power is given back to the PCB the RTCC continues from the time the main power supply was removed from the board, rather than the time now.

Reading the datasheets, I should not need to configure anything in order to have the RTCC keep time when using the SOSC. I also cannot find the flag RTCBAT to check this is set (the datasheet says this should be set to 1 by default) to ensure RTCC operaton with VBAT is enabled.

Below is my Config code and clock configuration from the setup routine.

// CONFIG4
#pragma config DSWDTPS = DSWDTPS1F // Deep Sleep Watchdog Timer Postscale Select bits (1:68719476736 (25.7 Days))
#pragma config DSWDTOSC = LPRC // DSWDT Reference Clock Select (DSWDT uses LPRC as reference clock)
//#pragma config DSBOREN = ON // Deep Sleep BOR Enable bit (DSBOR Enabled)
#pragma config DSBOREN = OFF // Deep Sleep BOR Enable bit (DSBOR Disabled)
//#pragma config DSWDTEN = ON // Deep Sleep Watchdog Timer Enable (DSWDT Enabled)
#pragma config DSWDTEN = OFF // Deep Sleep Watchdog Timer Enable (DSWDT Disabled)
#pragma config DSSWEN = ON // DSEN Bit Enable (Deep Sleep is controlled by the register bit DSEN)
#pragma config PLLDIV = DIVIDE2 // USB 96 MHz PLL Prescaler Select bits (Oscillator input divided by 2 (8 MHz input))
#pragma config I2C1SEL = DISABLE // Alternate I2C1 enable bit (I2C1 uses SCL1 and SDA1 pins)
#pragma config IOL1WAY = OFF // PPS IOLOCK Set Only Once Enable bit (The IOLOCK bit can be set and cleared using the unlock sequence)

// CONFIG3
#pragma config WPFP = WPFP127 // Write Protection Flash Page Segment Boundary (Page 127 (0x1FC00))
//#pragma config SOSCSEL = ON // SOSC Selection bits (SOSC circuit selected)
#pragma config SOSCSEL = OFF // SOSC Selection bits (Digital (SCLKI) mode)
#pragma config WDTWIN = PS25_0 // Window Mode Watchdog Timer Window Width Select (Watch Dog Timer Window Width is 25 percent)
#pragma config PLLSS = PLL_PRI // PLL Secondary Selection Configuration bit (PLL is fed by the Primary oscillator)
#pragma config BOREN = ON // Brown-out Reset Enable (Brown-out Reset Enable)
#pragma config WPDIS = WPDIS // Segment Write Protection Disable (Disabled)
#pragma config WPCFG = WPCFGDIS // Write Protect Configuration Page Select (Disabled)
#pragma config WPEND = WPENDMEM // Segment Write Protection End Page Select (Write Protect from WPFP to the last page of memory)

// CONFIG2
#pragma config POSCMD = EC // Primary Oscillator Select (External-Clock Mode Enabled)
#pragma config WDTCLK = LPRC // WDT Clock Source Select bits (WDT uses LPRC)
#pragma config OSCIOFCN = ON // OSCO Pin Configuration (OSCO/CLKO/RA3 functions as I/O)
#pragma config FCKSM = CSDCMD // Clock Switching and Fail-Safe Clock Monitor Configuration bits (Clock switching and Fail-Safe Clock Monitor are disabled)
#pragma config FNOSC = PRIPLL // Initial Oscillator Select (Primary Oscillator with PLL module (XTPLL,HSPLL, ECPLL))
#pragma config ALTRB6 = APPEND // Alternate RB6 pin function enable bit (Append the RP6/ASCL1/PMPD6 functions of RB6 to RA1 pin functions)
#pragma config ALTCMPI = CxINC_RB // Alternate Comparator Input bit (C1INC is on RB13, C2INC is on RB9 and C3INC is on RA0)
#pragma config WDTCMX = WDTCLK // WDT Clock Source Select bits (WDT clock source is determined by the WDTCLK Configuration bits)
#pragma config IESO = ON // Internal External Switchover (Enabled)

// CONFIG1
#pragma config WDTPS = PS32768 // Watchdog Timer Postscaler Select (1:32,768)
#pragma config FWPSA = PR128 // WDT Prescaler Ratio Select (1:128)
#pragma config WINDIS = OFF // Windowed WDT Disable (Standard Watchdog Timer)
//#pragma config FWDTEN = ON // Watchdog Timer Enable (WDT enabled in hardware)
#pragma config FWDTEN = OFF // Watchdog Timer Enable (WDT enabled in hardware)
#pragma config ICS = PGx1 // Emulator Pin Placement Select bits (Emulator functions are shared with PGEC1/PGED1)
#pragma config LPCFG = OFF // Low power regulator control (Disabled - regardless of RETEN)
#pragma config GWRP = OFF // General Segment Write Protect (Write to program memory allowed)
#pragma config GCP = OFF // General Segment Code Protect (Code protection is disabled)
//#pragma config JTAGEN = ON // JTAG Port Enable (Enabled)
#pragma config JTAGEN = OFF // JTAG Port Enable (Diabled)





// Clock Configuration

// RTC
    NVMKEY = 0x55; // Unlock RTC registers part 1
    NVMKEY = 0xAA; // Unlock RTC registers part 2
   
    RCFGCALbits.RTCWREN = 1; // Registers can be written by user
   
    RCFGCALbits.RTCEN = 0; // Disable RTC
   
// NVMKEY = 0x55;
// NVMKEY = 0xAA;
   
// RCFGCALbits.RTCWREN = 1; // Registers can be written by user
   
    RCFGCALbits.RTCSYNC = 0; // Registers can be read without concern of rollover ripple
    //RCFGCALbits.HALFSEC; // Half second status bit
    RCFGCALbits.RTCOE = 0; // RTCC Clock output disabled
    //RCFGCALbits.RTCPTR; // RTCC Value register pointer bits
    RCFGCALbits.CAL = 0; // Drift calibration 0
   
    ALCFGRPTbits.ALRMEN = 0; // Disable alARM
    ALCFGRPTbits.CHIME = 1; // Chime is enabled. Roll over allowed.
    //ALCFGRPTbits.AMASK = 0; // Alarm every half second
    //ALCFGRPTbits.AMASK = 1; // Alarm every 1 second
    ALCFGRPTbits.AMASK = 2; // Alarm every 10 seconds
    ALCFGRPTbits.ARPT = 255; // Repeat 255 times
   
    RTCPWCbits.PWCEN = 0; // Power control is disabled
    //RTCPWCbits.PWCPOL
    //RTCPWCbits.PWCCPRE = 0;
    //RTCPWCbits.PWCSPRE = 0;
    //RTCPWCbits.RTCCLK = 1; // Clock source is LPRC
    RTCPWCbits.RTCCLK = 0; // Clock source is SOSC


    IFS3bits.RTCIF = 0; // Clear interrupt flag
    IPC15bits.RTCIP = 2; // Set Interrupt priority 2
    IEC3bits.RTCIE = 1; // Enable Interrupt
   
    //ALCFGRPTbits.ALRMEN = 0; // Disable alarm
    ALCFGRPTbits.ALRMEN = 1; // Enable alarm
    RCFGCALbits.RTCEN = 1; // Enable RTC
    RCFGCALbits.RTCWREN = 0; // Registers cannot be written by user


Any suggestions what I'm doing wrong? I'm sure it's something simple!

If I use the LPRC as the clock source in place of the SOSC the clock works perfectly. I found the LPRC clock source to gain / lose time by up to an hour in a 24 hour period, so I'm keen to switch back to the SOSC.