EEPROM和NOR闪存之间的差异

主要的区别是Flash只能在块中被擦除。EEPROM是字节可擦除的。因此，Flash可获得更大（高达10倍），更便宜，更快速（和10X的SPI版本）。数据保持和“可靠性”是相同的。EEPROM的优势（除了字节擦除）是它忍受更多的写/擦除周期10X。2MBIT闪存可能有4K字节的擦除扇区，但是您可以单独写入每个字节。所以底线是，Flash可以存储日志和配置数据。如果数据填充了芯片并且需要环绕到先前写入的区域，那么在大的块中有明确擦除的复杂性，而不是擦除周期自动发生在字节基础上。没有什么大不了的，但比EEPROM要复杂得多。并且使用更大的闪存芯片可以完全消除正常操作中擦除的需要。



      以下为原文

    The main difference is that Flash can only be erased in blocks. EEPROM is byte erasable. As a result, Flash is available bigger (by up to 10x), cheaper, and faster (>10x for SPI versions). Data retention and "reliability" are the same. EEPROM advantage (besides byte erase) is that it endures more write/erase cycles by 10x.
 
A 2Mbit flash might have erase sectors of 4Kbyte, but you can write each byte individually. So the bottom line is that yes, Flash can store logs and configuration data. If the data fills the chip and needs to wrap around to previously written areas, you have the complication of explicitly erasing in large blocks rather than having the erase cycle happen on a byte basis automatically. Not a big deal, but more complicated than EEPROM. And using a bigger flash chip might eliminate the need for erasing during normal operation altogether.
 

我希望这个帖子能和“NAND”Flash讨论“不”，而不是Flash和EEPROM。



      以下为原文

    I was hoping that this thread was to discuss "NOR" vs. "NAND" Flash, rather than Flash vs. EEprom

@布朗宁，谢谢你那极好的洞察力朋友！你把事情弄得一清二楚，原谅我的无知…但我记得在某个地方读过，Flash是字节可寻址的，而不是NAND Flash。这是真的吗？还是我的记忆没有起作用？这给我带来了一个问题，应该让辛齐格高兴吗？For和NAND闪存的区别究竟是什么？为什么一个喜欢一个胜过另一个？最佳阿南德奖



      以下为原文

    @mbrowning, Thanks for that excellent insight friend! You have made the whole thing quite clear. 
Pardon me for my ignorance though.... but I remember reading somewhere that NOR flash is byte addressable as against NAND Flash which is not. Is this true? or my memory does not serve right? 
Which brings me to a question which should probably make Ms CinziaG happy?! What exactly is the difference between NOR and NAND flash?? Why would one prefer one over the other?
best regds Anand

你可能想考虑FRAM的使用。这是一个奇妙的技术，允许逐字节编程，没有块擦除所需的，有更高的写入耐久性数字，即使适用，仍然是非易失性。哦，还有一部分……没有长写时间。阅读和写作本质上是相同的时机。目前我使用的是FRAM，我以前使用的是I2C串行EEPROM，所以我使用的是带有I2C接口的FRAM，但是其他接口是可用的。我将留给您决定FRAM设备当前可用的密度是否是S。可用于日志记录应用程序。



      以下为原文

    You may want to consider the use of FRAM. It is a wonderful technology that allows byte by byte programming, no block erase needed, has way higher write endurance figures if even applicable, and is still non-volatile. Oh and another part....no long write times. Reading and writing are essentially the same timing.
 
Currently I am using FRAM for applications where I previously used I2C serial EEPROMs so am using the FRAMs with I2C interface but other interfaces are available.
 
I'll leave it to you to decide if currently available densities of FRAM devices are suitable for your logging application.

弗拉姆整洁。RAM的速度和接近无限循环耐力的访问。比EEPROM更贵，也没有那么大。根据您对组件成本的宽容，它可以是一个很好的选择。Flash是字节可寻址的读写，但只有块和芯片可擦除。一般来说，擦除设置位为1，将清除位写入0。实际上，您可以多次写入字节，但0位将保持0.NAND本质上是串行存储器（串行字节，而不是位），所以它被设计用于块访问。NAND在某些方面是有问题的。不能保证每个字节都是好的，除非通常在第一个块中。随着时间的推移，比特可能变差（就像硬盘一样）。在我的经验中，它只在OS管理它时使用——标记坏块并维护文件系统（无论是原始NAND还是EMMC芯片，还是SD卡）。如果你需要大量的存储和硬件和软件来驱动它，它可能是最便宜的选择。



      以下为原文

    FRAM is neat. RAM like speed and access with nearly unlimited cycle endurance. More expensive than eeprom, and not as big as NOR. Depending on your tolerance for component cost it could be a very good choice.
 
NOR Flash is byte addressable for reads and writes, but only block and chip erasable. Generally, erasing sets bits to 1, writing clears bits to 0. You can actually write bytes multiple times but 0 bits will stay 0.
 
NAND is inherently a serial memory (serial bytes, not bits) so it is designed for block access. NAND is problematic in some ways. You are not guaranteed every byte is good except usually in the first block. Bits can go bad over time (just like a hard disk). In my experience it's only used when an OS is managing it - marking bad blocks and maintaining a file system (whether it's raw NAND or eMMC chips, or SD cards). If you need lots of storage and have the hardware and software to drive it, it might be the cheapest choice.

通常使用的EEPROM也不是字节可寻址、字节可擦除和字节可写的。也不使用标准接口，例如字节并行、I2C或SPI直接访问存储器。也没有存储器比NAND更敏感地要求磨损均衡，但是在绝对可靠性要求的情况下，它确实需要引入某种形式的磨损均衡、冗余和/或刷新内容。NAND是通常用于固态盘、USB存储棒等的NAND写入和读取。作为一个512位至4096位数据字节的串行位流，根据实际的CHIP。NAND的实际字节数具有更高的密度，但由于此，它也倾向于有位故障，因此它也有一堆CRC位标记在每行上，还有一些用于SIG的位。如果行是好行或不行（也就是说，当良可以用于存储时，否则它有太多的错误以具有故障安全存储）。一个NAND处理芯片将管理CRC计算，允许在读取上纠正位错误，并管理坏行。在USB驱动器中，这都是由USB接口芯片处理的。在SSD中，它由SATA（或其他接口模式）芯片处理，使得CRC错误和坏点映射对用户来说都是不可见的。NAND存储器的可靠操作也需要磨损均衡，这也是由USB或SSD控制器处理的，因此对用户也是不可见的。我不清楚闪存通常使用的芯片如PICS是NOR还是NAND，但我相信它也不像闪光灯似乎没有。NAND具有的磨损均衡等问题（并且在NAND处理程序的文档中没有提及），但是其他的妥协例如写入周期的数量有限，并且在写入新数据之前需要特定的擦除步骤。擦除功能也在一行字节（最多64字节的一些芯片）上运行，而不是单个字节或字。我假设这减少了所需的芯片面积，因为通常不需要单字节擦除/写入。它还允许它们使存储单元更小，允许更小的芯片，但这是折衷减少擦除/写入周期的数目，这通常不是问题。我的理解是，使用一些闪存来模拟板上EEPROM的芯片（而不是像早期16F芯片那样具有特定EEPROM区域）在保留EEPROM仿真的区域中具有MiFiFig单元，以允许更高数量的擦除/写入周期，但仍有局限性。要求行擦除。



      以下为原文

   
NOR is what is normally used for EEPROM as it is byte addressable, byte erasable and byte writable. NOR memory is directly accessible using a standard interface such as byte parallel, I2C or SPI. Nor memory is less sensitive than NAND to requiring wear levelling, but where absolute reliability is required it does pay to introduce some form of wear levelling, redundancy and/or refresh of contents. 
 
NAND is what is normally used for Solid State Disks, USB memory sticks etc. NAND writes and reads a row as a serial bit stream of 512 to 4096 data bytes at a time, the actual number of bytes depending on the actual chip. NAND has much higher density, but as a result of this it also tends to have bit failures, so it also has a heap of CRC bits tagged on each row as well as some bits used to signal if a row is a good row or not (i.e. when good can be used for storage, otherwise it has too many errors to have failsafe storage). A NAND handling chip will manage the CRC calculations that will allow corrections of bit errors on reads, and also manage the bad rows. In a USB drive this is all handled by the USB interface chip. In an SSD it is handled by the SATA (or other interface mode) chip so that CRC errors and bad spots mapping is all invisible to the user. Reliable operation of NAND memory also requires wear leveling, which is also handled by the USB or SSD controller, and so is also invisible to the user.
 
It is unclear to me if the Flash memory normally used chips such as PICs is NOR or NAND, but I believe it is NOR as the Flash doesn't seem to have the problems of wear levelling etc that NAND has (and no mention is made in documentation of a NAND handler), but other compromises are made such as limited number of write cycles, and requiring a specific erase step before writing new data. The erase function also operates on a row of bytes (up to 64 bytes in some chips) rather than a single byte or word. I presume this reduces the die area required as single byte erase/write is not normally required. It also allows them to make the memory cells smaller allowing smaller die, but this is where the trade off is reduced number of erase/write cycles, which is not normally a problem. My understanding is that chips that use some of the Flash memory to emulate onboard EEPROM (rather than having a specific EEPROM area as early 16F chips have) have mofiifed cells in the area reserved for EEPROM emulation to allow a higher number of erase/write cycles, but still have the limitation of requiring row erase.