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我在过去的1个月里对PIC32 MK进行了评估（其中有一个健康的假期），外设看起来很有希望，但是我似乎无法让它以最大速度运行。我首先注意到它比以前的DSPIC33 EP慢。我用一个输出和一个作用域来测试100个指令（DMA配置，没有分支，但SFR使用），它看起来大约40M指令/s，看起来PCACH不工作了。？？？？？？！我试着用一个和谐来运行一个例子，但是如果我试图遵循教程并调用板配置器，我在MPLAB X中只会有例外。（仍然2.0.3BTW，下载2.0.4，但必须仍然尝试），所以使用数据表和PIC32 MX外设LIBS，我试图创建自己的SysSt配置性能，我猜SysCLK＝120 MHz是好的（因为PB2 1:1，SPI的除数似乎是合乎逻辑的）。大多数似乎都是OK的，除了它是缓慢的。我尝试撤销寄存器，它们似乎是OkCONFIG位：α-PrimLoMult＝Mule60，FPLLLKK＝PLLYPOSC，FPLLIDEV＝DIVIO1，FPLLoDIV= DIVIO4，FWDTEN= OFF，FPLLRNG＝RangeEy5510MHz MHz，PrimaMac配置PASCMOD＝HS，FNOSCC＝SPLL，DMCTCNT＝DMT31，FDMT，FDMT。EN＝OFF，DDSDTEN＝OFF，PMDL1WORE＝OFF，IOL1WORE＝OFF，ICESEL＝ICSU-PGX3，JTAGEN＝OFFOW 8MHz晶体/FPLLIDEV＝1×FPLLMULT＝60 /FPPLIDEV＝4＝8×60/4＝120个实际寄存器：PRISS:0x100000 7使用阴影集1用于我最常用的中断检测：0x07000，13PeCHEN＝1 DCHEN＝1 IcHEEN＝1 PREFEN＝1 PFMWS＝3（如指定为120时钟）PB1DIV:0x000 90088 PB2DIV:90008900PB3DIV:90008900PB4DIV:90008900PB5DIV:90008900PB6DIV：00008803个30 MHz MAX，但仅用于DSCON（深度睡眠），RTCC（实时时钟）无关？PB7DIV：读取OnLyfC016，0:A4210583XX3= kSeG0，指令预取缓存（推荐）OSCCon：00201102 sOSCEN＝1SO，我可能丢失了一些东西，但是什么？任何线索、洞察力、事物都要检查吗？
以上来自于百度翻译 以下为原文 I've evaluating the pic32mk for the last 1 1/2 month (with a healthy holiday somewhere in it), and the peripherals looks promising. However I can't seem to get it to run at max speed. I first noticed it was slower than the previous dspic33ep. I benchmarked about hundred instructions (DMA configuration, no branches, but SFR usage) using an output and a scope, and it seems to do about 40M instructions/s, iow it seems the pcache is not working?!?!?! I tried to run an example with hARMony, but I only got exceptions in MPLab X if I tried to follow the tutorials and invoke the board configurator. (still 2.0.3b btw, have download 2.0.4 but must still try) So using datasheets and the pic32MX peripheral libs I tried to create my own sysconfigperformance, and my guess is that the SYSCLK=120MHz is good (since with PB2 1:1 the divisors for SPI seem logical). Most seems to work ok, except that it is slow. I tried to dump the registers , and they seem to be ok config bits: #pragma config FPLLMULT = MUL_60, FPLLICLK =PLL_POSC ,FPLLIDIV = DIV_1, FPLLODIV = DIV_4, FWDTEN = OFF, FPLLRNG=RANGE_5_10_MHZ #pragma config POSCMOD = HS, FNOSC = SPLL, DMTCNT=DMT31, FDMTEN= OFF, DSWDTEN =OFF, FDSEN=OFF, PMDL1WAY = OFF,IOL1WAY=OFF,ICESEL = ICS_PGx3, JTAGEN = OFF iow 8MHz crystal /FPLLIDIV=1 * FPLLMULT=60 / FPPLODIV=4 = 8*60/4=120 actual registers: PRISS : 0x10000000 7 uses shadowset 1 for my most used interrupt CHECON: 0x07000013 percheen=1 dcheen=1 icheen=1 prefen=1 PFMWS=3 (as specified for 120 clock) PB1DIV: 0x00008800 PB2DIV: 00008800 PB3DIV: 00008800 PB4DIV: 00008800 PB5DIV: 00008800 PB6DIV: 00008803 30 MHz max but only used for DSCON (deep sleep),RTCC (realtime clock) unrelated ? PB7DIV: read only mfc0 16,0: A4210583 xxx3 = kseg0, Instruction Pre-fetch cached (Recommended) OSCCON: 00201102 SOSCEN=1 So I'm probably missing something, but what ? Any clues, insights, things to check? 
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嗨，你有PIC32 MK初学者工具包（（D320106）吗？我认为对于这个初学者工具包，在V2.04中有几个例子。您可以检查现有的项目来验证配置位是如何初始化的。
以上来自于百度翻译 以下为原文 Hi, Do you have a PIC32MK starter kit ( (DM320106) ? I think there are a couple of examples in Harmony v2.04 for this starter kit. You can check the existing projects to verify how configuration bits are initialized Regards |
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不，我认为SysCLK是好的，因为SPI速度是我所期望的。（与PB & LT；N＆GT；CLK配置如上）。我怀疑有什么东西能阻止帕奇。我试着看MK系统部分的和谐2.0.3，但没有发现很多新的。是的，如果我有剩余的时间，我会更新和睦，并试图找出更多，但第一次尝试并没有真正使我有信心。它看起来很脆弱，而且图书馆几乎不可读。
以上来自于百度翻译 以下为原文 No. Note that I think sysclk is good since the SPI speed is what I expect it to be. (with PB Yes, if I have some time to spare I will update Harmony and try to find out more, but the first attempt didn't really make me confident about it. It seems fragile, and the libraries are pretty near unreadable. |
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只是为你的芯片做一个空的和谐项目。使用时钟设置向导。这将允许它设置振荡器和高速缓存。看看它做了什么。
以上来自于百度翻译 以下为原文 Just make an empty harmony project for your chip. Use the clock setup wizard. This will allow it to setup the ocilator and the cache. See what it does. |
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勘误表表示预取器可能导致内存错误，应该禁用。我想这就是你所观察到的。
以上来自于百度翻译 以下为原文 Errata says prefetcher can cause memory errors and should be disabled. I guess this is what you observe. |
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NKurzman：正如我所说的，这是重新测试的计划，但我没有太多的希望。从我所看到的和谐，结果是不是很可读（与每一个CPU的每一个功能在外围图书馆等的文件）。这意味着我必须让它在我的自定义板上运行，例如串行到转储值。诺思盖尔：我好像没有这个自动取款机。我从一开始就没有速度，不只是不可靠，但是你是正确的，因为这一点（比DSPICE慢）A1 Rev是不可用的。它似乎只影响预测比特。（CeCH.PrEFEN），而PCACHE（CeCHO.PyCHEN）仍然可以启用（例如，加速线性代码）。我试着跟随勘误表，它甚至减慢了+/- 10%。它的长度大约是DSPICE上相似代码的两倍（并且相关代码的某些部分甚至使用EDS指针）。120兆赫？198个DMIPS？你在哪里？
以上来自于百度翻译 以下为原文 NKurzman: as said that is the plan to retest, but I don't have much hope. From what I've seen of harmony, the result is not very readable (with an include file per cpu per function in the peripheral library etc). This means I would have to get it actually running on my custom board with e.g. serial to dump values. Northguy: I don't seem to have this atm. I don't get the speed from the start, not just unreliability, but you are right that the A1 rev is unusable due to this (slower than the dspice). Also it seems to only affect the predictive bit. (checon.prefen), while the pcache (checon.percheen) still can be enabled (e.g. to accelerate linear code). I tried to follow the errata and it got even +/- 10% slower. It takes roughly twice as long as similar code on dspice (and there parts of the relevant code are even using eds pointers). 120MHz? 198 DMips? Where are thou ? |
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你不必使用所有的和声。它不是全部或没有。你可以用它来设置时钟和缓存，没有别的。在这一点上，你可以完成。或者，如果你喜欢PLib，你可以使用和声版本的PLIB。
以上来自于百度翻译 以下为原文 You do not have to use all of Harmony. It is Not all or nothing. You can use it to set up the Clock and Cache and nothing else. At that point you can be done. Or,You could then use Harmony's version of PLib if you liked PLib. |
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如果你的代码大部分是SFR寄存器访问（因为它是一个设置程序，那么它听起来是这样），那么它可能会很慢。对SFR来说，它可以读取或写入多个周期，并且预取缓存不会有太大的帮助（根本不需要SFR访问）。尝试一些正常的代码，很少有SFR访问，也可能是一些琐碎的数学循环。
以上来自于百度翻译 以下为原文 If much of your code is SFR register access (as it is a set-up routine then it sounds like it is) then it probably will be slow. It can take multiple cycles to read/write to an SFR, and the prefetch cache won't be helping much (not at all for the SFR accesses). Try some normal code with few SFR accesses, and perhaps some trivial math in a loop. |
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作为PIC32的第一次测试，我实现了WiZnet W5500 IP /以太网支持。最初我这样做是为了能够从更高的SPI速度中受益，但事实证明，用我现在的设置进行测试是不实际的（不是Microchip的错误、电路板布局以及我们将它附加到逻辑分析仪上的方式使它不可靠）。然而，在测试和调试时，我们注意到了。逻辑分析仪上的各种DMA分组之间的间隙大于60MHz DSPICE。（像8US，而不是5US），所以我们开始调查。测试代码是这样的间隙的一部分，为下一个DMA操作重置一些SPI和DMA寄存器，然后触发它。几乎所有的SFR访问都是存储（XXSETSE= Y或恰好XX＝Y）；它大约是40条指令，并且需要大约116个定时滴答（我用一个输出和一个范围来验证是基于一个120 MHz的基础锁），但是因为只有3个指令中只有1个在SFR上运行，所以SFR存储13个SFR+。26＝116，SFR Access＝大约7个周期。我用300个NOPS做了同样的事情，得到300个滴答，300个NoP，PrPoFix= 1（不稳定的A1每一个错误），600个PrimFoN＝0，所以PrPoFix= 1。CPU运行全倾斜。在基准NOPS的同时，我还增加了LAT清除和LAT设置（2X 3仪器）。UCTES，其中2个存储LATA），并测量了14个蜱的差异，每个LATASET/CLR STRIEI中大约有5个蜱在大开关语句中做了一些缓冲解码，并且也比DSPICE慢。PS是100%慢）我提出的结果，管理决策是把PIC32 MK在冰上。（因为我们将需要至少一代的DSPICE HW之前的新修订的MK表面）。如果我有更多的时间，我会尝试孤立其他代码片段的SFR不那么密集的基准。（下一轮的协议译码、移位寄存器等）。
以上来自于百度翻译 以下为原文 As a first test of PIC32 I implemented wiznet W5500 IP/ethernet support. Originally I did that to be able to benefit from higher SPI speeds, but it turned out that was not practical to test that with the setup I have now(not Microchip's fault, board layout and the way we attach it to the logic analyser makes it unreliable). However while testing and debugging we noticed the gaps between the various DMA packets on the logical analyser were larger than the 60MHz dspice. (like 8us instead of 5us), so we started investigating. The tested piece of code is part of such gaps, resetting of some spi and dma registers for the next DMA operation and then triggering it. Nearly all SFR access are stores (xxxSET=y or just xx=y); It's about 40 instructions and takes about 116 timer ticks ( which I verified with an output and a scope to be based on a 120MHz baseclock) However since only 1 in 3 instructions only operates on a SFR, so that would make the SFR store 13*sfr+26=116, sfr access= is about 7 cycles each. I did the same with just 300 nops, and I get 300 ticks for 300 nops with PREFEN=1 (unstable per errata for A1), and 600 with PREFEN=0 So with PREFEN=1 the CPU does run full tilt. While benchmarking the nops I also added a lat clear and a lat set (2x 3 instructions, 2 of them storing LATA), and measured the difference, 14 ticks, so that would be about 5 ticks per LATASET/CLR store I do some buffer decoding in large switch statement, and that is also slower than dspice.The effect on PREFEN on such code is much less though (about 10% slower, while the NOPs are 100% slower ) I presented the results, and the management decision is to put PIC32mk on ice for now. (since we will need at least another generation of dspice hw before a new revision of the mk surfaces). If I have more time I'll try to isolate benchmarks of other pieces of code that are less SFR intensive. (protocol decoding, shift registers etc) for the next round. |
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似乎Rev A2支持PREFEN问题：WW1.MICCHIP.COM/DeLoSt/En/DeVICEDC/O9007737 C.PDF
以上来自于百度翻译 以下为原文 Seems rev A2 adresses the PREFEN issue: ww1.microchip.com/downloads/en/DeviceDoc/80000737C.pdf |
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我花了3个小时，试图找到如何选择缓存设置和睦没有运气，到目前为止！我想选择是否启用了“非工作”预取缓存，但是在配置器树中不存在校验寄存器。我错过了什么吗？问题2更一般：如果我购买新批的PIC32 MK，我怎么知道它们是修订版A2还是A1？在我购买它们之前，看起来好像是相同的零件号和MaseIKE和DigiKig等等…不要谢
以上来自于百度翻译 以下为原文 i have spent 3 hours trying to find how to choose the cache settings in harmony with no luck so far !! i want to select whether the "non-working" prefetch cache is enabled , but CHECON register is not present in the Configurator Tree !! am i missing something ?? question 2 is more general : if i am buying new batch of pic32mk , how can i know if they are revision A2 or A1 ? before i buy them , it seems the same part number and mouser and digikey , etc ... donot tell thanks |
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1。我使用了MX PyLB LIBS的部分移植到MK，所以对和声不太了解。2。由于性能问题，我用PIC32 MK停止了，决定基于DSPICE做另一个系列，让尘埃先解决。所以我还没有一个Rev A2。
以上来自于百度翻译 以下为原文 1. I used parts of the MX perib libs ported to MK, so don't know much about harmony. 2. because of the performance issues I stopped with pic32mk, and decided to make another series based on dspice, and let the dust settle first. So I don't have an Rev A2 yet. |
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