PIC18F25K42 i2c从器件识别地址但不会发送ACK

您是否将I2CXCNT寄存器设置为被转换的字节数？



      以下为原文

    Have you set the I2CxCNT register with the number of bytes that are being exchnaged? 

这是单程列车，不是交换车。“有什么主意吗？”这可能是一百万件事。



      以下为原文

    It's a one way train, not an exchange.
 
"Any ideas?"
It could be a million things.

PIC是奴隶，所以不知道需要多少字节。在接收到匹配的地址后，它被偷窃。不理解。ISR -无论是被写入还是读取，在访问适当的ADRIF部分（有一个匹配和ADB0中有一个匹配ADR0的数字）之后，它会转到NACK部分。在数据表页554，从接收到的步骤8，它会说：如果有任何预错误的错误条件，例如接收缓冲器溢出或传输缓冲器欠流错误，从将强制NACK和模块变为空闲。然而，在ERRbits中没有设置任何其他错误的比特。在文本传输中没有等价的段落，在地址匹配之后，我得到相同的NACK问题。



      以下为原文

    The PIC is the slave so doesn't know how many bytes to expect.
 
It's NACKing after receiving an address that matches. Don't understand.
 

 
// ADR 32;
I2C1ADR0 = 0x20;
// ADR 127;
I2C1ADR1 = 0xFE;
// ADR 0;
I2C1ADR2 = 0x00;
// ADR 0;
I2C1ADR3 = 0x00;
// TXU 0; CSD Clock Stretching enabled; ACKT 0; RXO 0; ACKDT Acknowledge; ACKSTAT ACK received; ACKCNT Acknowledge;
I2C1CON1 = 0x00;
// ABD enabled; GCEN disabled; ACNT disabled; SDAHT 300 ns hold time; BFRET 8 I2C Clock pulses; FME disabled;
I2C1CON2 = 0x00;
// CLK Fosc/4;
I2C1CLK = 0x00;
// CNT 0;
I2C1CNT = 0x00;
// CSTR Enable clocking; S Cleared by hardware after Start; MODE four 7-bit address; EN enabled; RSEN disabled;
I2C1CON0 = 0x80;

PIR2bits.I2C1RXIF=0;
PIR3bits.I2C1TXIF=0;
PIR3bits.I2C1EIF=0;
I2C1ERRbits.NACKIF=0;
PIR3bits.I2C1IF=0;
I2C1PIRbits.PCIF=0;
I2C1PIRbits.ADRIF=0;

PIE2bits.I2C1RXIE=1;//enable I2C RX interrupt
PIE3bits.I2C1TXIE=1;//enable I2C TX interrupt
PIE3bits.I2C1EIE=1;//enable I2C error interrupt
I2C1ERRbits.NACKIE=1;//enable I2C error interrupt for NACK
PIE3bits.I2C1IE=1;//enable I2C interrupt
I2C1PIEbits.PCIE=1;//enable I2C interrupt for stop condition
I2C1PIEbits.ADRIE=1;//enable I2C interrupt for I2C address match condition


I2C1PIR = 0;// ;Clear all the error flags
I2C1ERR = 0;
 

 
and the ISR - whether being written to or read from, after visiting the appropriate ADRIF section (there's a match and ADB0 is populated with a number that matches ADR0) it then goes to the NACK part.
 

 
void I2C1_ISR ( void )
{
 
uint8_t I2C1_data = 0x55;
if ((I2C1STAT1bits.RXBF)||(PIR2bits.I2C1RXIF)) // RXBF = receive buffer full; I2C1RXIF = interrupt for that
{
PIR2bits.I2C1RXIF=0;
I2C1_data = I2C1RXB; // clear the register quick!
}
if(1 == I2C1STAT0bits.R) // if address match READ bit is set
{
 
if (I2C1PIRbits.PCIF) // if a stop condition
{
I2C1PIRbits.PCIF=0;
PIR3bits.I2C1IF=0;
I2C1STAT1bits.CLRBF=1;//clear I2C1TXB and TXBE
}
if (I2C1ERRbits.NACKIF) // if a nack - then that's the end of the read
{
I2C1ERRbits.NACKIF=0;
PIR3bits.I2C1EIF=0;
I2C1STAT1bits.CLRBF=1;//clear I2C1TXB and TXBE
I2C1_StatusCallback(I2C1_SLAVE_READ_COMPLETED);
}
else if(PIR3bits.I2C1TXIF) // transmit interrupt
{
PIR3bits.I2C1TXIF=0;
// callback routine should write data into I2C1TXB

I2C1_StatusCallback(I2C1_SLAVE_READ_A_BYTE);

}
if (I2C1PIRbits.ADRIF) // if an address flag
{
I2C1PIRbits.ADRIF=0;
PIR3bits.I2C1IF=0;
I2C1_StatusCallback(I2C1_SLAVE_READ_SET_POINTER);
}
 
}
else if((I2C1PIRbits.ADRIF)) // ADDRESS interrupt flag (and and not a READ => WRITE)
{
I2C1PIRbits.ADRIF=0;
PIR3bits.I2C1IF=0;
// callback routine should prepare to receive data from the master
I2C1_StatusCallback(I2C1_SLAVE_WRITE_REQUEST);
}
else // a write and this is the DATA
{
I2C1_slaveWriteData = I2C1_data; // transfer the copy of the register to a global variable for treatment by callbacks
 
// callback routine should process I2C1_slaveWriteData from the master
I2C1_StatusCallback(I2C1_SLAVE_WRITE_UNDERWAY);
}
I2C1CON0bits.CSTR=0; // clock stretching....
 
}
 
 
 

 
In datasheet page 554, step 8 of slave reception, it does say:
 
If there are any previous error conditions, e.g. Receive buffer overflow or transmit buffer under- flow errors, Slave will force a NACK and the module becomes Idle. 
However there are no other bits set in ERRbits suggesting anything wrong. And there is no equivalent paragraph in the text on Slave Transmission, where I get the same NACK problem after address match.

仍然试图理解为什么在地址匹配之后进行打盹。P597数据表：NACKIF：NACK检测中断标志位1＝何时（SMA＝1μm MMA＝1），并且在BxNACKIF上检测到NACK也设置在任何TXWRE、RXRDE、TXUF、RXOVR位被设置时。0＝NACK没有设置NACK/Debug检测码。发送不匹配的从属AddiSerStSU和RXO（TXUF和RXOVR是上面给出的不正确名称）在CON1中，而不是STEXXWE，RXRE（TXWRE和RXRDE似乎也是不正确的名称）在STAT1中，也没有看到它们被设置。在从接收（7位寻址）描述中模式）在P55中没有提到在接收到地址之后读取缓冲器的任何义务（为了清除它）。这不是我习惯的。MCC生成的代码不尝试这样做。我尝试了在清除ADRIF等之后——读取Adress缓冲区并授权ACK:I2C1YODATA＝I2C1ADB0；I2C1CON1BITS.ACKDT＝1；但这似乎不起作用。（对我来说没有圣诞节。



      以下为原文

    Still trying to understand why Nacking after an address match.
 
p587 datasheet:
NACKIF: NACK Detect Interrupt Flag bit
1= When(SMA=1||MMA=1)and a NACK is detected on the bus
NACKIF is also set when any of the TXWRE, RXRDE, TXUF, RXOVR bits are set.
0 = No NACK/Error detected
NACKIF is not set by the NACK send for non-matching slave addresses 
 
TXU and RXO (TXUF and RXOVR are incorrect names given above) are in CON1 and are not being set
TXWE and RXRE (TXWRE and RXRDE seem to be incorrect names too) are in STAT1 and don't see them being set either.
 
In the description of Slave Reception (7-bit Addressing Mode) on p554 there's no mention of any obligation to read a buffer AFTER an address has been received (in order to clear it). Which is not what I'm used to. The MCC generated code doesn't try to do that.
 
I tried - after clearing ADRIF etc. - reading the Adress buffer and authorising an ACK:
 
I2C1_data = I2C1ADB0; 
I2C1CON1bits.ACKDT = 1;
 
But that didn't seem to work. ;(
 
No Christmas for me.

我通过箍，让I2C工作…没有去MCC附近的任何地方！这是主人，但可能有帮助…？http://www. eTea技术…RK-in进步。15200



      以下为原文

    I went through hoops to get I2C working... did not go anywhere near MCC ! this is master but may be of help ..?
https://www.electro-tech-...rk-in-progress.152004/

谢谢大家的鼓励。每一条隧道都有尽头，除非它是一个洞穴！当我看到PIC18F26K22的数据表用于7位从属接收时，它是一个清晰的杰作：100%个明确的“软件”应该在每一个阶段做什么。相比之下，PIC18F25K42的等效页面要长得多，是指更多的寄存器，至少对我来说，它不是。清楚应该做什么。我想能够把MCC代码作为一个功能存根，但不知道更多。BTW.它确实生成一些可以让你开心的主代码，但是只有一个版本没有中断。



      以下为原文

    Thanks @Les for the encouragement. There is an end to every tunnel - unless it's a cave!
 
When I look at the datasheet for PIC18F26K22 for 7bit slave reception it's a masterpiece of clarity: it's 100% clear what "software" is supposed to do at every stage.
 
By comparison, the equivalent page for the PIC18F25K42 is much longer, refers to many more registers and - at least to me - it's not clear what is supposed to be done. I'd like to be able to take the MCC code as a functioning stub, but don't know any more.... Btw. it does generate some Master code which might amuse you - but only a version without interrupts.

一些PIC RX缓冲器需要读取，如果IF可以重置，PiR2BIT。I2C1RXIF＝0；这是发生的吗？



      以下为原文

    Some pic RX buffers need to be read before the IF can be reset ,
PIR2bits.I2C1RXIF=0; is this happening ? 

因此，在两个地方，从缓冲区读取可能会发生（地址和数据写入时）在清除中断之前交换到读缓冲区：在这里，我的两条包含的行，因为在数据表中启用了时钟拉伸，而不是完全清楚，是否必须读取地址或是否读取它。只是徒劳无功



      以下为原文

    Worth a try.
 
So in the two places where a read from buffer might occur (address and data - when being written to) swapped to read buffer before clearing interrupt:

if ((I2C1STAT1bits.RXBF)||(PIR2bits.I2C1RXIF)) // RXBF = receive buffer full; I2C1RXIF = interrupt for that
{
I2C1_data = I2C1RXB; // clear the register quick!
PIR2bits.I2C1RXIF=0;

 
and here my two included lines since clock stretching is enabled and not totally clear in datasheet whether address MUST be read or if it's optional

else if((I2C1PIRbits.ADRIF)) // ADDRESS interrupt flag (and and not a READ => WRITE)
{
I2C1_data = I2C1ADB0; // reading address in case important
I2C1CON1bits.ACKDT = 1; // force ACK in case important - but don't get one anyway!

I2C1PIRbits.ADRIF=0;
PIR3bits.I2C1IF=0;

 
but to no avail

你看过TB3159了吗？我用它开发硕士I2C，发现它很容易56K42。它也有一个从属操作的部分，但我从来没有看过它，因为我不需要它。我从来没有使用过任何图片上的I2C。我在FPGA上开发了I2C接口，很多年前我对STM32和I2C有很差的经验。我发现K42 I2C接口是非常简单易懂和易于使用的（至少对于主模式）。



      以下为原文

    Have you looked at TB3159? I used it for developing master I2C and found it very easy on 56k42. It has a section on Slave operation also, but I never looked at it since I didn't need it.
 
I've never used I2C on any PIC before. I've developed I2C interfaces on FPGAs, and I had a very bad experience with STM32 and I2C many years ago. I found the K42 I2C interface to be very simple to understand and easy to work with (at least for master mode).

@ M布朗，那个应用程序。注意是走的路…谢谢！有东西在那里我永远猜不到，现在奴隶接收良好。最后一个脚踩在梯子上……我是不是很笨，还是有人很聪明地隐藏了相关信息？



      以下为原文

    @mbrowning, that app. note is the way to go.... Thanks a bunch!
 
There's stuff in there I would never have guessed and now slave receives just fine. Finally a foot on the ladder...
 
Am I just very stupid or is somebody very clever at hiding relevant information?

亲爱的，我需要实现一个N2C的主机与外部EEPROM和MC23017的通信。有谁的PIC18F56K42的I2C库？因为这个新的家庭有不同的设置从标准的微芯片的巴士。我试图遵循一个TB3159，但也许我做错了什么。谢谢事先和最好的问候。



      以下为原文

    dear all
I need to implement a n i2C master for the comunication with external eeprom a nd the MCP23017. Does anyone the I2C library for the pic18f56k42 ? because this new family has a different setting from the standard microchip for the bus.
 
I tried to follow the AN  TB3159 but maybe i make something wrong.
 
Thanks in advance and best regards