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PIC18F25K40,我公司使用的主要I2C通信是很差的选择/设计,几年后,我试图解决由于噪声问题导致的I2C通信错误,所以很有趣。我们不应该使用I2C进行板外通信,并且我们超过总线电容规格很多。我有很多硬件解决方案,但我的公司(很小)非常不愿意重新设计我们的硬件/通信。我尝试了主软件(TEMP)解决方案,当I2C线被锁上时,它复位(症状,而不是实际原因),但是我不能在嘈杂的Env中得到任何可靠的工作。熨斗。我决定将I2C转换为使用MSSP来敲击(在启动硬件更改之前耗尽所有的软件[TEMP]解决方案)。我只是在初始阶段,但我注意到总线电容很容易在规格内,现在我有点撞击I2C。使用相同的硬件设置(6FT电缆),我可以看到时钟线上的上升时间是122Ns,总线电容在108PF,与使用MSSP W相比。6FT电缆和相同的上拉电阻在1530pF,总线电容在1330pF。是否存在MSSP和BIT的母线电容差的原因?MSSP有内部过滤,这可能是原因吗?非常感谢您的任何建议或帮助。谢谢,Brad。
以上来自于百度翻译 以下为原文 First time poster here; Pic: PIC18f25k40 The main I2C communication my company uses was poorly selected/designed and years later I'm trying to fix I2C communication errors due to noise issues, so fun. We shouldn't be using I2C for off-board communication, and we exceed the bus capacitance spec by a lot. I have many hardware solutions, but my company (being small) is very reluctant for redesigning our hardware/communication. I've attempted main software (temp) solutions for resetting the I2C lines when they get locked up (symptom, not actual cause) but I cant get anything reliable to work in noisy environments. I've decided to convert our I2C from using the MSSP to bit-banging (exhausting all my software [temp] solutions before we start hardware changes....) . I am only in the initial stages, but right away I noticed that the bus capacitance is easily within spec now that I'm bit-banging I2C. Using the same hardware set-up (6ft cable), I can see that the raise time on the clocking lines is 122ns with bus capacitance at 108pF, compared to using the MSSP with 6ft cable and same pull-up resistors at 1.5us with bus capacitance at 1330pF. Is there a reason for the bus capacitance difference between MSSP and Bit-banging? Is the MSSP have internal filtering that could be the reason for this? Any suggestions or help would be greatly appreciated. Thanks, Brad |
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3个回答
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很难相信PIN电容会有很大的变化。在I2C模式中没有额外的上限,更可能是你的BIT-BANG软件驱动时钟引脚高而不是三点说明它。SDA信号表现出相同的上升时间变化吗?如果没有I2C外围设备做时钟拉伸,并且在I2C总线上没有其他主机,那么无论如何都不需要SCL是开漏的,所以无论如何,驱动时钟高(而不是三位用TIS位)更好。
以上来自于百度翻译 以下为原文 Difficult to believe there would be much change in pin capacitance. There's no extra cap switched in in I2C mode. More likely is that your bit-bang software is driving the clock pin high rather than tri-stating it. Does the SDA signal show the same rise time change? If none of the I2C peripherals do clock-stretching, and there's no other master on the I2C bus, then there's no need for SCL to be open-drain anyway, so driving the clock high (rather than tri-stating with the TRIS bit) is better anyway. |
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你可以慢下来直到它开始工作。对奴隶来说不重要。更强的拉起会有帮助。虽然它是硬件的变化,但它不是大的。
以上来自于百度翻译 以下为原文 You can slow it down until it starts working. Shouldn't matter for the slave. Stronger pull-up would help. Although it is a hardware change, it's not a big one. |
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当你的意思是“上升时间”时,你似乎在说“总线电容”。当然,你的电容不会仅仅通过改变软件而改变。正如M布朗建议的,你的代码可能不遵循I2C规范,并且驱动引脚高而不是浮动。如果没有你的奴隶I。“时钟拉伸”,然后允许在SCL线上这样做,但是你不应该在SDA上这样做。正如已经提出的,正确的解决方案是降低你的上拉电阻的值,因此它们拉得更重,并且如果需要的话,降低I2C时钟速度,以确保信号保持足够高的足够长。
以上来自于百度翻译 以下为原文 You seem to be saying "bus capacitance" when you mean "rise time". Of course your capacitance does not change simply by changing the software. As mbrowning suggested, your code is probably not following the I2C specification, and is driving pins high rather than floating them. If none of your slaves implement "clock stretching", then it's permissible to do this on the SCL wire, but you shouldn't be doing it on SDA. (i.e. driving high). As already suggested, the correct solution is to reduce the value of your pullup resistors so they pull up harder, and reduce the I2C clock speed if needed to ensure the signal stays high long enough. |
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