关于编译器优化的奇怪问题

我有一小段代码，基本上在3个32位数组中初始化3个值。编译后的代码让我好奇为什么这样做…这只是一个为什么处理器内部的问题，这会使它成为“最好”的方法。在DSPIC33 EPMC202优化中的X16 1.25被设置为“S”。我困惑的是目的W0（@ 2076，207C和2082）的后减量。这是32位的“清除”，所以源上的后增量为目的地EA设置W0，但是为什么随后减去目的地W0？为什么不这样做呢？它每次都这样做，即使W0将被加载下面的指令。加载到W0中的常量是每个数组的基地址（是的，每个数组都包含3个32位值）。这也可以用第二个CLR来完成吗？或者：或者，看起来这三种方式之间没有尺寸差异，但是间接MOVs看起来可能会招致1个周期的失速。



      以下为原文

    I have this small section of code which basically initializes 3 values in 3 32-bit arrays. The compiled code has me curious why it was done this way... This is just a why question of what's internal to the processor which would make this the "best" way.

X16 1.25 on a dspic33EPMC202
Optimization is set to "s"

1509:                          array1[const_index] = 0;
002072  218160     MOV #0x1816, W0
002074  EB0800     CLR [W0]
002076  781030     MOV [W0++], [W0--]
1510:                          array2[const_index] = array1[const_index];
002078  218220     MOV #0x1822, W0
00207A  EB0800     CLR [W0]
00207C  781030     MOV [W0++], [W0--]
1511:                          array_n1[const_index] = 0;
00207E  21FE80     MOV #0x1FE8, W0
002080  EB0800     CLR [W0]
002082  781030     MOV [W0++], [W0--]


What has me confused is the post-decrement of destination W0 (@2076, 207C, and 2082) . This is a 32-bit "clear" so the post-increment on the source sets up W0 for the destination EA, but why then post-decrement the destination W0? Why not do this?
MOV [W0++],[W0]
It does this every time even though W0 will be loaded with the following instruction. The constants loaded into W0 are the base address of each array (yes, each array holds 3 32-bit values).

Could this have also been accomplished with a second CLR? Either:
CLR [W0++]
CLR [W0++]
or:
CLR[w0++]
CLR[w0]
It appears there would be no size difference between the three ways, but the indirect MOVs looks like they may incur a 1 cycle stall.