什么是积分噪声？

半导体

以前在我们的博客“什么是LDO噪声？第一部分”中，我们讨论了噪声的含义，如何指定和讨论了低压差稳压器安森美半导体提供的超低噪声。
今天，我们将进一步详细介绍积分噪声的含义。
积分噪声值来自频谱噪声密度函数的积分。
但是，按功能表达任何曲线并将其集成起来太复杂了。
更容易将测量曲线分成小部分。
如果每个部分的频率差fn + 1-fn变为0，则所有贡献的总和等于函数的积分。
在实际测量中，实现零差fn + 1-fn是不可能的，但是可以使其接近零。
频谱噪声密度测量具有许多点，使我们能够获得良好的精度积分噪声并检测振荡峰值。
在我们的例子中，我们有6,400个点，频率范围为10 Hz  -  100 kHz。
频谱噪声密度曲线按6,399个间隔进行插值，并表示为VNOISE，AVG，n。
下图显示了NCP110 LDO稳压器的频谱噪声密度。
如果我们将NCP110 LDO稳压器的测量值插入到最后一个等式中，我们将得到积分噪声的结果，如下表所示。
尽管由于COUT值较高，频谱噪声密度曲线会移动到较低频率，但积分噪声会增加。
为什么会这样？
如下图所示，您可以看到它是因为与IOUT和COUT相关的峰值移动到10 Hz  -  100 kHz的范围，其中计算了积分噪声。
为什么不为某些LDO选择高输出电容值？
正如您所看到的，当输出电容值变高且输出电流变低时，与输出电流和输出电容相关的峰值会增大并进入10Hz  -  100kHz的有用频率范围。
高输出电容值，例如10uF，可改善瞬态响应。
更好的瞬态响应可能是使用高值输出电容的原因。
在此示例中，当使用更高输出电容时，NCP110具有振铃（超过1次下冲）和更长的建立时间，但仍然稳定。振铃导致峰值增加，积分噪声也增加，如下表所示。
NCP110 LDO稳压器设计用于较低输出电容值1uF，增加额外电容可改善瞬态响应，但会影响系统噪声性能。
积分噪声是表示LDO在特定频率范围内产生多少噪声的方式。
在设计清洁电源时，了解如何测量噪声以及系统级设计选择的影响非常重要。
请继续关注下一篇关于电源抑制比（PSRR）的文章，我们将讨论如何衡量这一点以及对系统级设计的影响。
在此期间，请查看我们的NCP110数据表，了解有关今天主题的更多信息。

以上来自于谷歌翻译

以下为原文

Previously in our blog, "What is LDO Noise? Part I" we discussed what noise means, how it is specified and discussed what Low Dropout Regulator's ON Semiconductor offers with ultra-low noise. Today, we will go further into detail about what integral noise means.
Integral noise value is derived from the integral of the spectral noise density function. However, it is too complicated to express any curve by function and integrate it. It is easier to divide the measured curve in small parts. If the frequency difference fn+1 – fn of each part goes to 0, then the sum of all contributions is equal to the integral of the function.

In a real measurement achieving a zero difference fn+1 – fn is not possible, but it is possible to make it close to zero. Spectral noise density measurement has many points which enables us to achieve good accuracy integral noise and detect oscillation peaks. In our case, we have 6,400 points for a frequency range of 10 Hz – 100 kHz. The spectral noise density curve is interpolated by 6,399 intervals and expressed as VNOISE,AVG,n.

The picture below shows spectral noise density of  the NCP110 LDO Regulator. If we insert the measured values of the NCP110 LDO Regulator into the last equation, we will get the results of integral noise as shown in the table below. Although the Spectral Noise Density curve moves to a lower frequency because of the higher value of COUT the integral noise increases. Why does this happen? As the picture below demonstrates, you can see it is because the peak related to IOUT and COUT moves to the range of 10 Hz – 100 kHz in which integral noise is calculated.

Why not choose a high value of output capacitor for some LDOs? As you can see the peak, related to output current and output capacitor, grows and moves into the useful freqency range 10Hz – 100kHz when an output capacitor value goes higher and the output current goes lower.
A high value of output capacitor, for example 10uF, improves transient response. Better transient response might be a reason for using a of high value output capacitor. In this example NCP110 has ringing (more than 1 undershoot) and longer settling time to a transient event when using a higher output capcitor, but it still stable. The ringing causes the peak to increase and the integral noise also increase as shown in the table below. The NCP110 LDO Regulator is designed for a lower output capacitor value of 1uF and adding the additional capacitance improves transient response but impacts the system noise performance.

Integral noise is way of expressing how much noise an LDO makes in a specific frequency range.  Understanding how this noise is measured and the impact of system level design selections are important when designing a clean power supply.  Stay tuned for the next article on Power Supply Rejection Ratio (PSRR) where we will discuss how this is measured and the impacts on system level design. In the meantime check out our NCP110 datasheet for more information on today's topic.

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