许多汽车电源架构需要上游负载点（POL）转换，特别是高级/自主驾驶辅助系统（ADAS）应用，其中许多片上系统（SoC）和数字信号处理器（DSP）的低核心电压
超越了今天的开关模式电源（SMPS）最大转换率或主开关最小关断时间能力。
POL转换通常涉及从主电池连接的轨道电压向下转换到特定负载所需的较低的次级电压轨。
也可能需要其他应用和负载相关的属性，例如低噪声，高PSRR或高水平的负载瞬态响应。
但是，在电池连接的初级转换器的上游添加辅助电源可能会导致问题。
许多辅助导轨由线性调节器提供。
通常情况下不需要考虑功耗，并且需要优化噪声和电源抑制比（PSRR），例如，可能需要为噪声敏感的RF电路供电。
即使最初关注功耗，通常也可以从主电源产生中间轨电压，以允许使用线性稳压器作为次级电源。
在这种情况下，即使是非常高的负载电流水平也可以由低噪声线性稳压器支持，但是具有非常低的压降电压。
NCP59300和NCP59748是高电流（分别为3.0 A和1.5 A）线性稳压器的示例，具有低噪声特性和极低的压差。
特别是NCP59748实现了最大165 mV的压差电压。
通过为两者提供单独的输入，主要通过将电源路径与内部电路偏置分开（图1）。
这允许偏置输入从较高电压轨输出，并且电源路输入从较低电压轨输出到源，使得线性稳压器刚好保持在其脱落状态之上，从而最小化功耗。
图1 - 具有独立Vin和Vbias源的NCP59748
在许多应用中，效率和功耗是主要问题，使用次级SMPS，其中次级SMPS的输入电流加载主SMPS的输出。
通过暗示，连接到次级的负载应该不太容易受到SMPS产生的噪声的影响，否则需要采用额外的输出滤波。
在辅助转换器加载初级转换器的输出的情况下，需要考虑两者之间的相互作用以及任何额外的中间滤波。
如果次级转换器的大容量输入电容位于物理上靠近初级转换器输出的位置，那么初级转换器的大容量输出电容可以按比例减小，同时仍保持相同的纹波和环路响应性能。
然而，通常长板迹线或甚至线束将两个转换器互连，使大容量电容器去耦合并提供中间滤波。
在这种情况下，没有大容量电容减小的好处，但是需要注意中间滤波器的阻抗负载效应，无论是寄生还是其他，否则会导致上游转换器的稳定性问题。
未能将输入滤波器阻抗保持低于SMPS输入阻抗的阻抗可能导致振荡。
在次级POL转换器的输出处，高电容水平可能导致另一个问题。
将SMPS设置为具有一定残余电压的部分或完全充电的输出电容可能导致SMPS吸收通过低端MOSFET的电流。
因此，需要使用NCV6323同步降压转换器或NCV894630开关模式稳压器中的负电流限制来保护低端MOSFET不发生故障。
在多个次级转换器加载初级转换器并且次级转换器具有允许振荡器同步的同步输入的情况下，则可以使用相位定位来交错次级转换器的振荡器的时序。
这对于具有不连续输入电流的降压转换器尤其有利，因为它们的高侧开关导致高纹波电流并且因此需要大的体积输入电容器来进行滤波。
相移它们的开关消除了输入电流的重叠，从而消除了输入纹波，从而减小了所需输入滤波器的尺寸。
实际上，一些初级转换器，例如NCV890101，提供相移180度的从同步输出，可用于同步多个初级转换器，或初级和次级转换器，同相，但使用相同的基频
。
将所有转换器同步到相同的基频，通过将所有开关锁定到相同的频率而没有偏差来实现电磁发射。
图2 - 两个主转换器，主设备同步从设备
以上来自于谷歌翻译
以下为原文
Many automotive power supply architectures require upstream point-of-load (POL) conversion, particularly Advanced/Autonomous Driver Assistance Systems (ADAS) applications where the low core voltage of many System-On-Chips (SoC) and Digital Signal Processors (DSP) are beyond todays Switched Mode Power Supply’s (SMPS) maximum conversion ratio or main switch minimum off-time capability. POL conversion typically involves down conversion from a primary, battery connected rail voltage to a lower secondary voltage rail required by a particular load. Other application and load dependent attributes may be required too, such as low noise, high PSRR or high levels of load transient response. However, adding secondary power supplies upstream of the battery connected primary converter can lead to issues.
Many secondary rails are provided by a linear regulator. This is often the case where power dissipation is not a concern and noise and Power Supply Rejection Ratio (PSRR) need to be optimized, perhaps where powering noise sensitive RF circuitry for instance. Even where power dissipation is initially of concern, very often an intermediate rail voltage can be created from the primary power supply to allow the use of a linear regulator as the secondary supply. In which case even very high load current levels can be supported by a low noise linear regulator, but one with a very low drop-out voltage. The NCP59300 and NCP59748 are examples of high current (3.0 A and 1.5 A respectively) linear regulators with a low noise characteristic yet very low drop-out voltages. The NCP59748 in particular achieves a drop-out voltage of just 165 mV max. at 1.5 A, largely by separating the power path from the internal circuit biasing, by the provision of separate inputs for both (Fig. 1). This allows the bias input to source from a higher voltage rail and the power path input to source from a lower voltage rail, such that the linear regulator is just held above its drop-out condition, minimizing power dissipation.
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Fig. 1 – NCP59748 with separate Vin and Vbias sources
In many applications where efficiency and power dissipation are a major concern, secondary SMPSs are used, where the input current of the secondary SMPS loads the output of the primary SMPS. By implication the loads connected to the secondary should be less susceptible to the noise produced by the SMPSs, otherwise additional output filtering needs to be employed.
Where a secondary converter loads a primary converter’s output, the interaction between the two, and any additional intermediate filtering, needs to be considered. If the secondary converter’s bulk input capacitance is located physically close to the output of the primary converter then the primary converter’s bulk output capacitance can be reduced pro rata, while still retaining the same ripple and loop response performance. However, typically long board traces, or even harnesses, interconnect the two converters, de-coupling the bulk capacitors and providing intermediate filtering. In this case there is no benefit of bulk capacitance reduction but the impedance loading effect of the intermediate filter, whether parasitic or otherwise, needs to be heeded - otherwise it can cause stability issues for the upstream converter. Failure to keep the input filter impedance below that of the input impedance of the SMPS can lead to oscillations.
A further issue can be caused by high capacitance levels, at the output of the secondary POL converter. Enabling an SMPS into a partially or fully charged output capacitor with some residual voltage can cause the SMPS to sink the current through the low side MOSFET. As a result a negative current limit, such as that employed in the NCV6323 synchronous buck converter or the NCV894630 switch-mode regulator is required to protect the low side MOSFET from failure.
Where multiple secondary converters load a primary converter, and the secondary converters have a synchronization input to allow oscillator synchronization, then phase positioning can be used to interleave the timing of the secondary converter’s oscillators. This is particularly of benefit to buck converters which have discontinuous input current, due to their high-side switch, leading to high ripple currents and requiring a large bulk input capacitor to filter as a result. Phase shifting their switching eliminates the overlap of input currents and as a result input ripples, thereby reducing the size of the required input filter. Indeed some primary converters, such as the NCV890101, provide a slave synchronization output, phase shifted by 180 degrees, which can be used to synchronize either multiple primary converters, or the primary and its secondary converter, out of phase yet utilizing the same fundamental frequency. Synchronizing all converters to the same fundamental frequency, has electro-magnetic emissions benefits by keeping all switching locked to the same frequency without deviation.
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Fig. 2 – Two primary converters with the Master synchronizing the Slave
So while linear regulators can be used for high current POL conversion, conferring some benefits for particular applications over and above an SMPS - where an SMPS is required then consideration should be given to protecting the converter from high output capacitances, input filter mismatch and interleaving.
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