PIC32从空闲复位类型唤醒可能导致此问题的原因是什么？

我有一个包含PIC32 MX664 F128H的系统，它控制几个电磁铁阵列的开关。在PCB设计中实现了对PIC的不稳定电源的所有“标准”预防措施（充足的去耦帽、4层PCB、信号到开关电路的光隔离、单独的电源连接和分/不共享的理由等）。是PIC在正常使用期间断续重置。这些重置发生在恒定操作的5到25分钟之间，并且没有特定的电磁开关序列可以确定为复位的原因。在一系列调试测试中，确定RCON寄存器中的空闲（唤醒空闲标志）位在启动时被设置。根据PIC的数据表，空闲状态是通过发布等待指令来实现的，这是我的源代码中任何地方都没有发生过的事情。似乎所有的东西都指向设备处于闲置状态，但它不合计。由于PCB布局包括对PIC的不稳定电源的一些预防措施，我对这可能是问题的严重怀疑。此外，BOR（Brown out Read）位在这样的重置期间从未设置，除了上电复位（连同POR位，这对于系统启动来说是完全正常的）。因为在我的源代码中没有等待指令，什么会导致PIC突然进入空闲状态？异常（比如堆栈溢出或堆栈下溢）会导致此重置事件吗？它还能与电力有关吗？模块配置中的某个东西会为这一事件打开大门吗？所使用的配置比特如下：使用的唯一中断是来自不同子系统的UART数据接收。但是，我不确定是否有一些随机中断标志可能在操作期间被设置（无意中），因为没有中断服务例程。



      以下为原文

    I have a system containing a PIC32MX664F128H that controls the switching of several arrays of electromagnets. All the "standard" precautions against an unstable power supply to the PIC have been implemented in the PCB design (ample decoupling caps, 4-layer PCB, optical isolation of signals to the switching circuitry, separate power connections and divided/unshared grounds, etc.).

The issue that I am facing is that the PIC resets intermittently during normal usage. These resets occur between 5 to 25 minutes of constant operation, and no particular sequence of electromagnet switching could be determined as the cause of the resets.

During a series of debugging tests it was determined that the IDLE (Wake From Idle Flag) bit in the RCON register was set at startup (after the reset occurred).

According to the PIC's datasheet, it seems that the idle state is achieved through issuing the WAIT instruction - something that never happens anywhere in my source code. Everything seems to point to the device being put into idle mode, but it just doesn't add up. Since the PCB layout includes a number of precautions against an unstable power supply to the PIC, I have serious doubts that this could be the issue. Furthermore, the BOR (brown-out reset) bit is never set during such a reset, except for a power-on reset (along with the POR bit, which is totally normal for a system startup).

Since there is no WAIT instruction in my source code, what could cause the PIC to suddenly go into the idle state? Could an exception (like a stack overflow or stack underflow) cause this reset event? Could it still be power related? Could something in the configuration of the module open a door to this happening? The configuration bits as used are given below:

// DEVCFG3
//#pragma config PMDL1WAY = OFF // Peripheral Module Disable Configuration (Allow multiple reconfigurations)
//#pragma config IOL1WAY = OFF // Peripheral Pin Select Configuration (Allow multiple reconfigurations)
//#pragma config FUSBIDIO = OFF // USB USID Selection (Controlled by the USB Module)
//#pragma config FVBUSONIO = OFF // USB VBUS ON Selection (Controlled by USB Module)
// DEVCFG2 /* see DEFINES section for further details on oscillator configuration */
#pragma config FPLLIDIV = DIV_2 // PLL Input Divider (2x Divider)
#pragma config FPLLMUL = MUL_20 // PLL Multiplier (20x Multiplier)
#pragma config FPLLODIV = DIV_1 // System PLL Output Clock Divider (PLL Divide by 2)
//#pragma config UPLLIDIV = DIV_1 // USB PLL Input Divider (12x Divider)
//#pragma config UPLLEN = OFF // USB PLL Enable (Disabled and Bypassed)
// DEVCFG1
#pragma config FNOSC = FRCPLL // Oscillator Selection Bits (Fast RC Osc with PLL (FRCPLL))
#pragma config FSOSCEN = OFF // Secondary Oscillator Disnable (Disabled)
#pragma config IESO = ON // Internal/External Switch Over (Enabled)
#pragma config POSCMOD = OFF // Primary Oscillator Configuration (Primary osc disabled)
#pragma config OSCIOFNC = OFF // CLKO Output Signal Active on the OSCO Pin (Disabled)
#pragma config FPBDIV = DIV_1 // Peripheral Clock Divisor (Pb_Clk is Sys_Clk/1)
#pragma config FCKSM = CSECMD // Clock Switching and Monitor Selection (Clock Switch Disable, FSCM Disabled)
#pragma config WDTPS = PS1048576 // Watchdog Timer Postscaler (1:1048576)
//#pragma config WINDIS = OFF // Watchdog Timer Window Enable (Watchdog Timer is in Non-Window Mode)
#pragma config FWDTEN = OFF // Watchdog Timer Enable (WDT Disabled (SWDTEN Bit Controls))
//#pragma config FWDTWINSZ = WISZ_25 // Watchdog Timer Window Size (Window Size is 25%)
// DEVCFG0
//#pragma config JTAGEN = OFF // JTAG Enable (JTAG Disabled)
#pragma config ICESEL = ICS_PGx1 // ICE/ICD Comm Channel Select (Communicate on PGEC1/PGED1)
#pragma config PWP = OFF // Program Flash Write Protect (Disable)
#pragma config BWP = OFF // Boot Flash Write Protect bit (Protection Disabled)
#pragma config CP = OFF // Code Protect (Protection Enabled)

The only interrupt used is for UART data reception from the a different subsystem. However, I am not sure if some random interrupt flag could potentially (and unintentionally) be set during operation, for which there is no interrupt service routine.

Any help would be greatly appreciated.