18F65K40：UART2闲置低

我有一个奇怪的问题与UART2在18F65 K40。我在这个芯片上使用所有5个UART，而其他4个则正常运行。但只有UART2 TX闲置低。我处于异步模式，SCKP没有影响。这几乎就像SCKP被困在高硅，我不能改变它。我看不到任何关于这件事的勘误表。以前有人见过这样的东西吗？这是我的最低可行代码。它输出0xAA每500毫秒的发射引脚。我运行了一个16MHz晶体的芯片，并启用PLL。一个有趣的调试尝试，我尝试将所有的寄存器从UART2到UART1（以及适当的PPS的东西）。这样，我可以使用完全相同的代码来观察UART1的TX线。UART1正确地闲置高。



      以下为原文

    I'm having a strange issue with UART2 on an 18F65K40. I'm using all 5 UARTs on this chip and the other 4 are behaving normally. But just UART2 TX idles low. I'm in asynchronous mode and SCKP has no affect. It's almost like SCKP is stuck high in the silicon and I can't change it. I don't see anything in the errata about this.

Has anyone seen something like this before? Here's my minimum viable code. It outputs 0xAA every 500ms out the transmit pin. I run the chip off a 16MHz crystal and enable PLL.

One interesting debugging attempt I tried was to change all of the registers from UART2 to UART1 (along with the appropriate PPS stuff). In that way, I could observe UART1's TX line using the exact same code. UART1 properly idled high.

#pragma config FEXTOSC = HS // External Oscillator mode Selection bits (Oscillator not enabled)
#pragma config RSTOSC = HFINTOSC_1MHZ// Power-up default value for COSC bits (HFINTOSC with HFFRQ = 4 MHz and CDIV = 4:1)

// CONFIG1H
#pragma config CLKOUTEN = OFF // Clock Out Enable bit (CLKOUT function is disabled)
#pragma config CSWEN = ON // Clock Switch Enable bit (Writing to NOSC and NDIV is allowed)
#pragma config FCMEN = ON // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor enabled)

// CONFIG2L
#pragma config MCLRE = EXTMCLR // Master Clear Enable bit (If LVP = 0, MCLR pin is MCLR; If LVP = 1, RG5 pin function is MCLR )
#pragma config PWRTE = OFF // Power-up Timer Enable bit (Power up timer disabled)
#pragma config LPBOREN = OFF // Low-power BOR enable bit (ULPBOR disabled)
#pragma config BOREN = SBORDIS // Brown-out Reset Enable bits (Brown-out Reset enabled , SBOREN bit is ignored)

// CONFIG2H
#pragma config BORV = VBOR_2P45 // Brown Out Reset Voltage selection bits (Brown-out Reset Voltage (VBOR) set to 2.45V)
#pragma config ZCD = OFF // ZCD Disable bit (ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON)
#pragma config PPS1WAY = ON // PPSLOCK bit One-Way Set Enable bit (PPSLOCK bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle)
#pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
#pragma config DEBUG = OFF // Debugger Enable bit (Background debugger disabled)
#pragma config XINST = OFF // Extended Instruction Set Enable bit (Extended Instruction Set and Indexed Addressing Mode disabled)

// CONFIG3L
#pragma config WDTCPS = WDTCPS_31// WDT Period Select bits (Divider ratio 1:65536; software control of WDTPS)
#pragma config WDTE = OFF // WDT operating mode (WDT Disabled)

// CONFIG3H
#pragma config WDTCWS = WDTCWS_7// WDT Window Select bits (window always open (100%); software control; keyed access not required)
#pragma config WDTCCS = SC // WDT input clock selector (Software Control)

// CONFIG4L
#pragma config WRT0 = OFF // Write Protection Block 0 (Block 0 (000800-001FFFh) not write-protected)
#pragma config WRT1 = OFF // Write Protection Block 1 (Block 1 (002000-003FFFh) not write-protected)
#pragma config WRT2 = OFF // Write Protection Block 2 (Block 2 (004000-005FFFh) not write-protected)
#pragma config WRT3 = OFF // Write Protection Block 3 (Block 3 (006000-007FFFh) not write-protected)

// CONFIG4H
#pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-30000Bh) not write-protected)
#pragma config WRTB = OFF // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
#pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected)
#pragma config SCANE = ON // Scanner Enable bit (Scanner module is available for use, SCANMD bit can control the module)
#pragma config LVP = ON // Low Voltage Programming Enable bit (Low voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE configuration bit is ignored)

// CONFIG5L
#pragma config CP = OFF // UserNVM Program Memory Code Protection bit (UserNVM code protection disabled)
#pragma config CPD = OFF // DataNVM Memory Code Protection bit (DataNVM code protection disabled)

// CONFIG5H

// CONFIG6L
#pragma config EBTR0 = OFF // Table Read Protection Block 0 (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR1 = OFF // Table Read Protection Block 1 (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR2 = OFF // Table Read Protection Block 2 (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR3 = OFF // Table Read Protection Block 3 (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks)

// CONFIG6H
#pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)

#include

#define _XTAL_FREQ 64000000

void main(void) {

    asm("BSF NVMCON1,7");

    OSCCON1bits.NOSC = 0b010; //FEXTOSC with 4x PLL
    OSCCON1bits.NDIV = 0b0000; //No divider

    TRISGbits.TRISG0 = 0;
    TRISGbits.TRISG1 = 1;
    RX2PPS = 0b110000 | 1;
    RG0PPS = 0x0F;

    ANSELG = 0;

    BAUD2CONbits.SCKP = 0;  //<-No affect??
    TX2STAbits.SYNC = 0;
    TX2STAbits.TX9 = 0;
    RC2STAbits.RX9 = 0;
    PIE3bits.TX2IE = 0;
    PIE3bits.RC2IE = 0;
    TX2STAbits.BRGH = 1;
    BAUD2CONbits.BRG16 = 1;
    SP2BRG = 0x14;
    SP2BRGH = 0x01;

    TX2STAbits.TXEN = 1;
    RC2STAbits.CREN = 1;
    RC2STAbits.SPEN = 1;

    while(1)
    {
        while( !PIR3bits.TX2IF );
        TX2REG = 0b10101010;
        __delay_ms(500);
    }
}

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