vrf JTAG (again!)

来自Gregg C Levine的您好我们现在关于JTAG概念和VEE吗？
在发布此消息之前，我决定尝试使用Shawn的档案。但是这个主题只有17个？
其中一些人在我们身上有我的名字。基本上我打算调整上周为此目的讨论过的并行端口DLL。
硬件是调整Xilinix或相关公司当前工作的硬件之一。但我仍在寻找有关如何为此构建VEE程序的建议.---------- Gregg C Levine landocalrissian atsign
att dot net ~~这个Signature支持Rebel联盟恢复共和国~~“他们在错误的时间出错了，自然他们成了英雄。”
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     以下为原文

  Hello from Gregg C Levine
Where are we now regarding the JTAG concepts and VEE?

As it happens before posting this message I decided to try Shawn's archive.
Nice, but only 17 on the subject? And some of them had my name on them.

Basically I am planning on adapting the Parallel Port DLL that was discussed
here last week for that purpose. The hardware is one of adapting the current
one from Xilinix or related companies for the job.

But I'm still searching for advice concerning how to construct VEE programs
for this one.
----------
Gregg C Levine landocalrissian atsign att dot net
~~This Signature supports the Rebel Alliance to Restore The Republic~~
"They were in the wrong place at the wrong time, naturally they became
heroes."
Princess Leia Organa of Alderaan, Senator


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格雷格，你在为JTAG使用什么？
也就是说，如何从原理图中直接描述JTAG字符串？
另外，如何自动化内置测试。
TheASSET工具有一个很好的DLL，直接进入VEE。
那是在2000年;但是，我还没有看到他们更新的工具。
我不确定并行端口是最好的方法。
专用串口可能是最好的。
我不明白为什么你不能使用USB端口。
我记得使用双轨的问题（关于故障未显示的事情），因此可能需要转换器。
所以任何序列都可能有效。
你的巴斯速度将取决于你的被测设备，以及从PC到DUT的距离。
无论如何，我怀疑你需要一个转换器，要么掉到PC Buss上，要么连接到串口或并口总线。请注意你将使用I2C或其他JTAG端口，注意JTAG端口是串口，所以你需要
在你的并行接口修复此问题。
让我了解您认为哪种通信最好。
至于我，我更喜欢u***端口。不管怎样，你的问题是什么？Rufus未来，一次一个想法.-----原帖-----来自：Gregg C Levine [mailto：landocalrissian@att.net
发送时间：2004年12月5日星期日下午3点06分：VRFS主题：[vrf] JTAG（再次！）来自Gregg C Levine的您好我们现在关于JTAG概念和VEE吗？
在发布此消息之前，我决定尝试使用Shawn的档案。但是这个主题只有17个？
其中一些人在我们身上有我的名字。基本上我打算调整上周为此目的讨论过的并行端口DLL。
硬件是调整Xilinix或相关公司的工作人员的工作。但我仍在寻找有关如何为此建立VEE程序的建议.---------- Gregg C Levine landocalrissian atsign att
dot net ~~这个签名支持Rebel联盟恢复共和国~~“他们在错误的时间处于错误的位置，自然他们成了英雄。”
Alderaan公主Leia Organa，参议员---您目前订阅了vrf：rwarren@amti.net订阅发送ablank电子邮件至“join-vrf@it.lists.it.agilent.com”。要取消订阅发送空白
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     以下为原文

  Greg,

What are you using for JTAG?  That is, how do you describe the JTAG strings
directly from the schematic?  Also, how do you automate built-in tests.  The
ASSET tools have a nice DLL that drops right into VEE.  That was in 2000;
however, I have not seen their updated tools. 

I'm not sure the parallel port is the best way to go.  A dedicated serial is
probably best.  I don't see why you could not use the u*** port.  I remember
an issue of using dual rail(something about faults not showing), hence a
converter might be needed.  So any serial will probably work.  The speed of
your buss is going to depend upon your device under test, and the distance
from the PC to the DUT.  At any rate I suspect you will need a converter,
either dropped onto the PC Buss or hooked to a serial or parallel buss.
Suspect you'll use I2C or some other JTAG port, note the JTAG port is a
serial port so you will need to fix this at your parallel interface. 

Keep me informed on what kind of communications you think are best.  As for
me, I prefer the u*** port.

Anyway, what is your question?


Rufus

The future, one idea at a time.

-----Original Message-----
From: Gregg C Levine [mailto:landocalrissian@att.net]
Sent: Sunday, December 05, 2004 3:06 PM
To: VRF
Subject: [vrf] JTAG (again!)

Hello from Gregg C Levine
Where are we now regarding the JTAG concepts and VEE?

As it happens before posting this message I decided to try Shawn's archive.
Nice, but only 17 on the subject? And some of them had my name on them.

Basically I am planning on adapting the Parallel Port DLL that was discussed
here last week for that purpose. The hardware is one of adapting the current
one from Xilinix or related companies for the job.

But I'm still searching for advice concerning how to construct VEE programs
for this one.
----------
Gregg C Levine landocalrissian atsign att dot net ~~This Signature supports
the Rebel Alliance to Restore The Republic~~ "They were in the wrong place
at the wrong time, naturally they became heroes."
Princess Leia Organa of Alderaan, Senator


---
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st1：* {behavior：url（#default＃ieooui）} Greg，At Herley我们使用Xilinx和Altera FPGA作为驱动电路的基础，并作为所有一致性数据的容器。
作为VEE开发人员，我一直致力于为我们的RF和微波器件自动化编程和一致性过程。
我绝不是JTAG专家，但在这种情况下，我没有成功。例如：我们利用Quartus作为我们Xilinx设备上的开发工具。
我们可以从命令行访问其综合工具。
Alteras也支持这个过程。
与设计工程师合作我能够开发批处理文件以自动化Quartus固有的编程算法。我们还开发了一个将所有配置文件放在特定文件夹中的系统。
在此示例中，在进行VEE自动一致性测量后，我使用此唯一信息重建指定的“* .ucf”文件。我使用上述批处理文件和重新编译的配置文件重新编程驱动程序。
最后，我扫描在这个过程中创建的错误日志中的错误。它不漂亮，但它的工作原理。
参见www.Xilinx.com Michael FordTest EngineeringHerley Farmingdale425 Smith Street Farmingdale，NY 11735-1198631.630.2000 ext 268（传真）631.630.2066mailto：Michael.Ford@Herley.com -----原始消息-----来自：
Gregg C Levine [mailto：landocalrissian@att.net]发送时间：2004年12月5日星期日下午3点06分：VRFS主题：[vrf] JTAG（再次！）你好Gregg C Levine我们现在关于JTAG概念和VEE吗？
在发布此消息之前，我决定尝试Shawn'sarchive.Nice，但只有17个主题？
其中一些人在我们身上有我的名字。基本上我打算调整上周为此目的讨论的并行端口DLL。
硬件是调整来自Xilinix或相关公司的当前人员的工作。但我仍在寻找有关如何为此构建VEE程序的建议.---------- Gregg C Levine landocalrissian atsign att dot net
~~这个签名支持Rebel联盟恢复共和国~~“他们在错误的时间出错了，自然他们成了英雄。”
Alderaan的Leia Organa公主，参议员---您目前订阅了vrf：MFord@Generalmicrowave.com订阅时发送空白电子邮件至“join-vrf@it.lists.it.agilent.com”。要取消订阅发送空白
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     以下为原文

  st1:*{behavior:url(#default#ieooui) }Greg,At Herley we use Xilinx and Altera FPGA's as a basis for our drivercircuits and as a container for all conformance data. As the VEE developer I wastasked to automate the programming and conformance process for our RF andMicrowave devices. I am by no means a JTAG expert, but in this case, I didn'tneed to be. For example: We utilize Quartus as the development tool on our Xilinxdevices. We are able to access its synthesis tools from the command line. Alterasupports this process as well. Working with Design Engineers I was able todevelop Batch files to automate the programming algorithms inherent to Quartus.We also developed a system of placing all configuration files in specificfolders. In this example, after taking VEE automated conformance measurements,I rebuild a specified "*.ucf" file utilizing this unique information.I reprogram the driver utilizing the above mentioned batch files and the recompiledconfiguration files. At the end, I scan for errors in error logs created inthis process. It's not pretty, but it works. See www.Xilinx.com    Michael FordTest EngineeringHerley Farmingdale425 Smith Street Farmingdale, NY 11735-1198631.630.2000 ext 268 (fax) 631.630.2066mailto:Michael.Ford@Herley.com    -----Original Message-----
From: Gregg C Levine [mailto:landocalrissian@att.net]
Sent: Sunday, December 05, 2004 3:06 PM
To: VRF
Subject: [vrf] JTAG (again!) Hello from Gregg C LevineWhere are we now regarding the JTAG concepts and VEE?  As it happens before posting this message I decided to try Shawn'sarchive.Nice, but only 17 on the subject? And some of them had my name on them. Basically I am planning on adapting the Parallel Port DLL that wasdiscussedhere last week for that purpose. The hardware is one of adapting thecurrent one from Xilinix or related companies for the job. But I'm still searching for advice concerning how to construct VEEprogramsfor this one.----------Gregg C Levine landocalrissian atsign att dot net ~~This Signature supports the Rebel Alliance to Restore The Republic~~ "They were in the wrong place at the wrong time, naturally theybecame heroes." Princess Leia Organa of Alderaan, Senator  ---You are currently subscribed to vrf as: MFord@Generalmicrowave.comTo subscribe send a blank email to"join-vrf@it.lists.it.agilent.com".To unsubscribe send a blank email to"leave-vrf@it.lists.it.agilent.com".To send messages to this mailing list,  email"vrf@agilent.com".  If you need help with the mailing list send a message to"owner-vrf@it.lists.it.agilent.com".---You are currently subscribed to vrf as: [email=r***@soco.agilent.com]r***@soco.agilent.com[/email]To subscribe send a blank email to "join-vrf@it.lists.it.agilent.com".To unsubscribe send a blank email to "leave-vrf@it.lists.it.agilent.com".To send messages to this mailing list,  email "vrf@agilent.com".  If you need help with the mailing list send a message to "owner-vrf@it.lists.it.agilent.com".