完善资料让更多小伙伴认识你,还能领取20积分哦, 立即完善>
大家好,在过去的几天里,我感到非常沮丧: - [与Momentum(ADS2006)一起开始怀疑我们是否已经做出了将这个工具全部放在一起的正确决定。
我想知道的是,是否有人能够使用至少4层模拟合理的复杂基板布局? 不是简单的电感器或发夹滤波器等。我的基板~8x6mm具有2个RF(约30个键合线)和基带(约90个键合线)。 也有一些被动物。 基本上是典型的SiP。 我的工作站是全新的64Bit戴尔8),4 GB内存,3.2GHz处理器,WinXP 64,我已经设置了100GB虚拟内存。 这台机器上也安装了很少的其他应用程序,基本上是一个干净的安装。很高兴知道其他工程师能够做什么。 谢谢, 以上来自于谷歌翻译 以下为原文 Hi All, Over the past few days I have getting pretty frustrated :-[ with Momentum (ADS2006) and am beginning to wonder if we have made the right decision in getting this tool all together. What I would like to know is if anyone has been able to simulate resonably complex substrate layouts with at least 4 layers? Not simple inductors or hairpin filters etc. My substrate ~8x6mm has and 2 die an RF (about 30 bond wires) and baseband (about 90 bond wires). There are a few passives too. Basically a typical SiP. My workstation is a brand new 64Bit Dell 8), 4 GB RAM, 3.2GHz processor, WinXP 64, I have setup 100GB virtual ram. There are very few other apps installed on this machine too, basically a clean installation. It would be good to know what other engineers have been able to do. Thanks, |
|
相关推荐
3个回答
|
|
嗨!您想要为整个模块建模吗?确保您可以在应用程序中使用动力。
然而,您的基板是相当大的8x6mm,有4层加上布局中复杂的阵容。 很难将其模拟到单个模拟设置中。在这种情况下我通常做的是,我将基板分成4个相等的部分,这样我就可以减小物理尺寸以及端口数量。 这样的动量可以阻止我的模拟的内存大小,“让你的电路更简单”。首先模拟基板然后使用TUDelf模型来模拟你的键合线。 这应该是很多工作肯定的。在可能的情况下,我已经能够使用ADS2005A的动量模拟器将整个PA模块8x8 mm建模为4层。 使用动量你需要更多的耐心来设置你的模拟bech但如果你设置正确,它会给你精确的结果。 以上来自于谷歌翻译 以下为原文 Hi! You want to model the whole module? For sure you can use momentum in your application. However your substrate is quite large 8x6mm with 4 layers plus complex line-ups in the layout. Its difficult to simulate that into a single simulation setup. What I normally do in that kind of situations was, I broke the substrate into 4 equal parts such that I can reduce the physical size as well as the number of ports. Such that the momentum can able to hundle the memory size of my simulation, "make you circuit less complicated". Model the substrate first then use TUDelf model to model your bondwires. That should be a lot of work for sure. In may cased I had been able to modeled the whole PA module 8x8 mm with 4 layers using momentum simulator of ADS2005A. Using momentum you need more patience for setting up your simulation bech but it will give you acurate results if you made you settings correct. |
|
|
|
是的,这将是理想的情况。
但我认为实际上我需要使用一些工程判断并将其分解以模拟我需要的位。 但危险的是,如果它被过度简化,那么它与真实模块不同。我的情况的一个大问题是布局不是源自ADS布局,而是由Cadence中的第三方完成。 因此,当您导入它时,物理形状很复杂。 特别是地平面间隙,这些是圆形的。 网格不喜欢这些! 在过去几天里,由于安捷伦应用工程师和服务台的帮助,我取得了一些进展。希望在我们的下一个模块中,我们将在ADS中完成所有工作!你提到了键合线的TUDelf模型,这里找到了 ? 我正在考虑使用所提供的飞利浦型号或尝试使用“空气桥”结构。感谢您的反馈。 知道其他人能做什么总是很好。但是, 以上来自于谷歌翻译 以下为原文 Yes, that would be the ideal scenario. But I think in reality I will need to use some engineering judgement and break things down to simulate the bits that I need. But the dangerous thing is, if it is over simplified it then is not the same as the real module. A big issue with my circumstance is that the layout does not originate from ADS layout, instead it was done by a 3rd party in Cadence. So when you import this, the physical shapes are complex. Particularly the ground plane clearances, these are circular. The mesher does not like these! Over the past few days I had some progress, thanks to the help from the Agilent application engineer and the help desk. Hopefully in our next module we will do it all in ADS! You mentioned TUDelf model for the bond wires, where is this found? I was thinking of using either the Philips models provided or try using an 'air bridge' structure. Thanks for your feedback. It is always nice to know what other people are able to do. regards, |
|
|
|
我见过客户用几十个非常薄的层(nm范围)模拟IC结构。
问题在于几何复杂性和整体电气尺寸。 您可以通过自己对这些多边形进行布尔运算并使用“首选项”>“输入/编辑”设置“最终最小顶点距离”来部分清理过于复杂的多边形.TU Delft键合线位于Passive-RF电路调色板的底部。 以上来自于谷歌翻译 以下为原文 I have seen customers simulate IC structures with dozens of very thin layers (nm range). The issue is with geometric complexity and overall electrical size. You can partially clean up overly complex polygons by doing Booleans of those polygons with themselves and using the Preference>Entry/Edit setting "Final Minimum Vertex Distance". The TU Delft bond wires are on the bottom of the Passive-RF Circuit palette. |
|
|
|
只有小组成员才能发言,加入小组>>
1291 浏览 0 评论
2375 浏览 1 评论
2194 浏览 1 评论
2065 浏览 5 评论
2952 浏览 3 评论
1123浏览 1评论
关于Keysight x1149 Boundary Scan Analyzer
758浏览 0评论
N5230C用“CALC:MARK:BWID?”获取Bwid,Cent,Q,Loss失败,请问大佬们怎么解决呀
934浏览 0评论
1294浏览 0评论
小黑屋| 手机版| Archiver| 电子发烧友 ( 湘ICP备2023018690号 )
GMT+8, 2024-12-26 07:02 , Processed in 1.307914 second(s), Total 81, Slave 65 queries .
Powered by 电子发烧友网
© 2015 bbs.elecfans.com
关注我们的微信
下载发烧友APP
电子发烧友观察
版权所有 © 湖南华秋数字科技有限公司
电子发烧友 (电路图) 湘公网安备 43011202000918 号 电信与信息服务业务经营许可证:合字B2-20210191 工商网监 湘ICP备2023018690号