简单的锁定看门狗定时器电路设计

Figure 1. This circuit produces a latched failure indication in response to a loss of input pulses.
During power-up, active-low RESET remains low until VCC stabilizes and the reset timeout delay expires. Capacitor C charges through R until the FET's gate voltage reaches its threshold (VTH), which turns on the FET and enables the latching capability. To prevent false triggers, you should set the delay of RC much longer than the reset timeout.
The WDI input (pin 6) must toggle at a minimum rate set by the capacitor CSWT. If that fails to happen, active-low RESET goes low, turns on the LED, and pulls the RESET IN connection low, thereby latching active-low RESET. The circuit remains in this condition until you cycle VCC or push the switch. Either action turns off the FET and allows RESET IN to go high.
To monitor the open-drain tachometer signal of a fan, connect a 10kΩ pullup resistor from WDI to VCC (pin 8), and connect WDI to the fan's tachometer output. Because the fan requires some time to spin up, the watchdog circuit needs to be deactivated for a short delay interval. You can create this delay by placing a capacitor (C2) from RESET IN to ground. Notice that this delay must be shorter than the RC delay mentioned above, or active-low RESET will latch prematurely.
For a fan monitor, the value of CSWT sets the maximum tachometer pulse period according to the formula tWD = 5.06 × 106 × CSWT, where tWD is in seconds and CSWT is in farads. If the fan speed drops below this threshold, the active-low RESET output asserts low and latches.