S5PV210实现uboot spl

ti

本帖最后由 lee_st 于 2018-4-27 08:23 编辑

S5PV210 启动过程需要 BL1， BL2，其中 BL1 进行一些基本初始化（时钟、内存），加载

BL2 到内存。 U-boot 为此专门实现了 SPL 框架。SPL 的全称为 secondary program loader，即第 2 阶段程序加载器，即我们要实现的 BL1。要支持 SPL，我们需要在单板配置文件 u-boot-2014.04/include/configs/smdkc100.h 定义宏 CONFIG_SPL。spl的整个运行过程：

1. 运行 arch/arm/cpu/armv7/start.S 文件，设置异常向量表，关闭中断，设置处理器到svc模式，然后执行cup_init_cp15这个段，从字面意思理解是初始化cp15。然后跳转到cpu_init_crit。在cpu_init_crit中调用 board/samsung/tiny210/lowlevel_init.S中lowlevel_init。

2. 在lowlevel_init中主要做了两件事情：system_clock_init和ddr_init。

3. 返回 arch/arm/cpu/armv7/start.S 中，然后跳转到函数_main，这个函数在u-boot-2014.04/arch/arm/lib/crt0.S中定义。

下面开始更改uboot

1、首先在 boards.cfg 文件第 379 行添加 smdkv210 配置参数Active arm armv7 s5pc1xx samsung smdkv210 smdkv210 - -总共 9 个参数，最后面是 2 个破折号。

2、复制文件

复制 includeconfigssmdkc100.h 为 smdkv210.h

复制 boardsamsungsmdkc100 文件夹为 boardsamsungsmdkv210

smdkv210 目录中的 smdkc100.c 改名为 smdkv210.c

修改 smdkv210 目录中 makefile 的第一行为：

obj-y := smdkv210.o

3、修改文件

1） includeconfigssmdkv210.h 文件中添加：

/*SPL config start*/

#define CONFIG_SPL

#ifdef CONFIG_SPL

/*define CONFIG_SPL_BUILD in makefile.spl*/

/*#define CONFIG_SPL_BUILD*/

#define CONFIG_SPL_FRAMEWORK

/*

* see Figure 8-3 in IMX6DQ/IMX6SDL Reference manuals:

* - IMX6SDL OCRAM (IRAM) is from 0x00907000 to 0x0091FFFF

* - IMX6DQ has 2x IRAM of IMX6SDL but we intend to support IMX6SDL as well

* - BOOT ROM stack is at 0x0091FFB8

* - if icache/dcache is enabled (eFuse/strapping controlled) then the

* IMX BOOT ROM will setup MMU table at 0x00918000, therefore we need to

* fit between 0x00907000 and 0x00918000.

* - Additionally the BOOT ROM loads what they consider the firmware image

* which consists of a 4K header in front of us that contains the IVT, DCD

* and some padding thus 'our' max size is really 0x00908000 - 0x00918000

* or 64KB

*/

#define CONFIG_SPL_TEXT_BASE 0xD0020010

#define CONFIG_SPL_MAX_SIZE (16 * 1024)

#define CONFIG_SPL_STACK 0xD0037D80

#define CONFIG_SPL_LIBCOMMON_SUPPORT

#define CONFIG_SPL_LIBGENERIC_SUPPORT

#define CONFIG_SPL_SERIAL_SUPPORT

#define CONFIG_SPL_GPIO_SUPPORT

/*#define CONFIG_MMC*/

/**/

#ifdef CONFIG_MMC

#define CONFIG_SPL_MMC_SUPPORT

#define CONFIG_GENERIC_MMC

#define CONFIG_PARTITIONS 1

#define CONFIG_SPL_LIBDISK_SUPPORT

#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address

0x60000 */

#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */

#endif

/**/

/* MMC support */

#endif

/*SPL config end*/

现在暂时不支持加载 uboot。

2）在/arch/arm/include/asm/arch-s5pc1xx/cpu.h 文件中添加 V210 的基址宏定义：

/* S5PV210 is same to S5PC110*/

#define S5PV210_PRO_ID 0xE0000000

#define S5PV210_CLOCK_BASE 0xE0100000

#define S5PV210_GPIO_BASE 0xE0200000

#define S5PV210_PWMTIMER_BASE 0xE2500000

#define S5PV210_WATCHDOG_BASE 0xE2700000

#define S5PV210_UART_BASE 0xE2900000

#define S5PV210_SROMC_BASE 0xE8000000

#define S5PV210_MMC_BASE 0xEB000000

#define S5PV210_DMC0_BASE 0xF0000000

#define S5PV210_DMC1_BASE 0xF1400000

#define S5PV210_VIC0_BASE 0xF2000000

#define S5PV210_VIC1_BASE 0xF2100000

#define S5PV210_VIC2_BASE 0xF2200000

#define S5PV210_VIC3_BASE 0xF2300000

#define S5PV210_OTG_BASE 0xEC000000

#define S5PV210_PHY_BASE 0xEC100000

#define S5PV210_USB_PHY_CONTROL 0xE010E80C

3） /arch/arm/include/asm/arch-s5pc1xx/lowlevel_init.S 文件修改：

添加头文件#include

将 system_clock_init 改为 V210 的初始化代码：
/*
* initialize core clock and bus clock.
*/
system_clock_init:
ldr r0, =0xe0100000
mov r1, #0xe00
orr r1, r1, #0x10
str r1, [r0, #0x00] //*(0xe0100000)=0xe10
str r1, [r0, #0x04] //*(0xe0100004)=0xe10
str r1, [r0, #0x08] //*(0xe0100008)=0xe10
str r1, [r0, #0x0c] //*(0xe010000c)=0xe10
ldr r1, =CLK_DIV0_VAL
str r1, [r0, #0x300] //*(0xe0100300)=((1<<0) | (7<<4) |(3<<8) | (1<<12) | (3<<16) |
(1<<20) | (4<<24) | (1<<28))
ldr r1, =CLK_DIV1_VAL
str r1, [r0, #0x304] //*(0xe0100304)=((1<<16) | (1<<12) |(1<<8) | (1<<4))
ldr r1, =CLK_DIV2_VAL
str r1, [r0, #0x308] //*(0xe0100308)=(1<<0)
ldr r1, =APLL_VAL
str r1, [r0, #0x0100] //*(0xe0100100)=((1<<31) | (APLL_MDIV<<16) |
(APLL_PDIV<<8) | (APLL_SDIV))
ldr r1, =MPLL_VAL
str r1, [r0, #0x0108] //*(0xe0100108)=((1<<31) | (MPLL_MDIV<<16) |
(MPLL_PDIV<<8) | (MPLL_SDIV))
ldr r1, =EPLL_VAL
str r1, [r0, #0x0110] //*(0xe0100110)=((1<<31) | (EPLL_MDIV<<16) |
(EPLL_PDIV<<8) | (EPLL_SDIV))
ldr r1, =VPLL_VAL
str r1, [r0, #0x0120] //*(0xe0100120)=((1<<31) | (VPLL_MDIV<<16) |
(VPLL_PDIV<<8) | (VPLL_SDIV))
mov r1, #0x10000
1: subs r1, r1, #1
bne 1b
mov pc, lr
初始化后， cpu 主频变为 1Ghz。
Msys-hclk = 200Mhz
Msys-pclk = 100Mhz
Dsys-hclk = 166Mhz
Msys-pclk = 83Mhz
psys-hclk = 133Mhz
psys-pclk = 66Mhz