转：FPGA学习之六位数码管驱动

FPGA

FPGA学习之六位数码管驱动
一、实验目的：实现六位数码管驱动，显示0-999999。
二、实验环境：FPGA开发板AX301,Quartus ii
三、实验介绍：通过取模模块得到每位的值，再转为为需要显示的二进制值，最后通过行、列扫描模块，点亮数码管。
如图：

前文：先介绍一下数码管显示原理
七段数码管原理及编码
我们最常用的是七段式和八段式LED数码管，八段比七段多了一个小数点，其他的基本相同。所谓的八段就是指数码管里有八个小LED发光二极管，通过控制不同的LED的亮灭来显示出不同的字形。数码管又分为共阴极和共阳极两种类型，其实共阴极就是将八个LED的阴极连在一起，让其接地，这样给任何一个LED的另一端高电平，它便能点亮。而共阳极就是将八个LED的阳极连在一起。其原理图如下。

其中引脚图的两个COM端连在一起，是公共端，共阴数码管要将其接地，共阳数码管将其接正5伏电源。一个八段数码管称为一位，多个数码管并列在一起可构成多位数码管，它们的段选线（即a,b,c,d,e,f,g,dp）连在一起，而各自的公共端称为位选线。显示时，都从段选线送入字符编码，而选中哪个位选线，那个数码管便会被点亮。数码管的8段，对应一个字节的8位，a对应最低位，dp对应最高位。所以如果想让数码管显示数字0，那么共阴数码管的字符编码为00111111，即0x3f；共阳数码管的字符编码为11000000，即0xc0。可以看出两个编码的各位正好相反。

数码管编码

共阳极的数码管0~f的段编码：

unsigned char code table[]={ //共阳极0~f数码管编码
0xc0,0xf9,0xa4,0xb0,//0~3
0x99,0x92,0x82,0xf8,//4~7
0x80,0x90,0x88,0x83,//8~b
0xc6,0xa1,0x86,0x8e //c~f
};
共阴极的数码管0~f的段编码是：

unsigned char code table[]={//共阴极0~f数码管编码
0x3f,0x06,0x5b,0x4f, //0~3
0x66,0x6d,0x7d,0x07, //4~7
0x7f,0x6f,0x77,0x7c, //8~b
0x39,0x5e,0x79,0x71 //c~f
};
参考地址：http://blog.sina.com.cn/s/blog_786f53750102x7jg.html

源码：
column_scan_module.v

module smg_scan_module
(
CLK, RSTn,
Hunthu_SMG_Data, Tenthu_SMG_Data,Thu_SMG_Data, Hun_SMG_Data,Ten_SMG_Data, One_SMG_Data,
Row_Scan_Sig, Column_Scan_Sig
);
input CLK;
input RSTn;
input [7:0] Hunthu_SMG_Data;
input [7:0]Tenthu_SMG_Data;
input [7:0]Thu_SMG_Data;
input [7:0]Hun_SMG_Data;
input [7:0]Ten_SMG_Data;
input [7:0]One_SMG_Data;
output [7:0]Row_Scan_Sig;
output [5:0]Column_Scan_Sig;
/*****************************/
row_scan_module U1
(
.CLK( CLK ),
.RSTn( RSTn ),
.Hunthu_SMG_Data( Hunthu_SMG_Data ), // input - from top
.Tenthu_SMG_Data( Tenthu_SMG_Data ), // input - from top
.Thu_SMG_Data( Thu_SMG_Data ), // input - from top
.Hun_SMG_Data( Hun_SMG_Data ), // input - from top
.Ten_SMG_Data( Ten_SMG_Data ), // input - from top
.One_SMG_Data( One_SMG_Data ), // input - from top
.Row_Scan_Sig( Row_Scan_Sig ) // output - to top
);
column_scan_module U2
(
.CLK( CLK ),
.RSTn( RSTn ),
.Column_Scan_Sig( Column_Scan_Sig ) // output - to top
);
/********************************/
endmodule

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number_mod_module.v

module number_mod_module
(
CLK, RSTn,
Number_Data,
Hunthu_Data,Tenthu_Data,Thu_Data,Hun_Data,Ten_Data, One_Data//定义十万万千百十个位
);
input CLK;
input RSTn;
input [19:0]Number_Data;
output [3:0]Hunthu_Data;
output [3:0]Tenthu_Data;
output [3:0]Thu_Data;
output [3:0]Hun_Data;
output [3:0]Ten_Data;
output [3:0]One_Data;
/*********************************/
reg [31:0]rHunthu;
reg [31:0]rTenthu;
reg [31:0]rThu;
reg [31:0]rHun;
reg [31:0]rTen;
reg [31:0]rOne;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
rHunthu <= 32'd0;
rTenthu <= 32'd0;
rThu<= 32'd0;
rThu<= 32'd0;
rHun<= 32'd0;
rTen <= 32'd0;//？高级版本中，除法器默认是32位的，经过“编译”后，编译器会自动优化到何时的位宽
rOne <= 32'd0;
end
else
begin
rHunthu<= Number_Data/100000;
rTenthu <= (Number_Data / 10000)%10;
rThu<= (Number_Data/1000)% 10;
rHun<= (Number_Data/100)% 10;
rTen <= Number_Data/10;
rOne <= Number_Data%10;
end
/***********************************/
assign Hunthu_Data = rTen[3:0];
assign Tenthu_Data = rOne[3:0];
assign Thu_Data = rTen[3:0];
assign Hun_Data = rOne[3:0];
assign Ten_Data = rTen[3:0];
assign One_Data = rOne[3:0];
/***********************************/
endmodule

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row_scan_module.v

module row_scan_module
(
CLK, RSTn,
Hunthu_SMG_Data, Tenthu_SMG_Data,Thu_SMG_Data, Hun_SMG_Data,Ten_SMG_Data, One_SMG_Data,
Row_Scan_Sig
);
input CLK;
input RSTn;
input [7:0] Hunthu_SMG_Data;
input [7:0]Tenthu_SMG_Data;
input [7:0]Thu_SMG_Data;
input [7:0]Hun_SMG_Data;
input [7:0]Ten_SMG_Data;
input [7:0]One_SMG_Data;
output [7:0]Row_Scan_Sig;
/*******************************/
parameter T10MS = 19'd499_999;//50M*0.01-1=499_999
/*******************************/
reg [18:0]Count1;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
Count1 <= 19'd0;
else if( Count1 == T10MS )
Count1 <= 19'd0;
else
Count1 <= Count1 + 19'b1;
/*******************************/
reg [3:0]t;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
t <= 3'd0;
else if( t == 3'd6 )
t <= 3'd0;
else if( Count1 == T10MS )
t <= t + 1'b1;
/**********************************/
reg [7:0]rData;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
rData <= 8'd0;
else if( Count1 == T10MS )
case( t )
3'd0 : rData <= Hunthu_SMG_Data;
3'd1 : rData <= Tenthu_SMG_Data;
3'd2 : rData <= Thu_SMG_Data;
3'd3 : rData <= Hun_SMG_Data;
3'd4 : rData <= Ten_SMG_Data;
3'd5 : rData <= One_SMG_Data;
endcase
/***********************************/
assign Row_Scan_Sig = rData;
/***********************************/
endmodule

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smg_encoder_module.v

module smg_encoder_module
(
CLK, RSTn,
Hunthu_Data,Tenthu_Data,Thu_Data,Hun_Data,Ten_Data, One_Data,
Hunthu_SMG_Data, Tenthu_SMG_Data,Thu_SMG_Data, Hun_SMG_Data,Ten_SMG_Data, One_SMG_Data
);
input CLK;
input RSTn;
input [3:0]Hunthu_Data;
input [3:0]Tenthu_Data;
input [3:0]Thu_Data;
input [3:0]Hun_Data;
input [3:0]Ten_Data;
input [3:0]One_Data;
output [7:0] Hunthu_SMG_Data;
output [7:0]Tenthu_SMG_Data;
output [7:0]Thu_SMG_Data;
output [7:0]Hun_SMG_Data;
output [7:0]Ten_SMG_Data;
output [7:0]One_SMG_Data;
/***************************************/
parameter _0 = 8'b1100_0000, _1 = 8'b1111_1001, _2 = 8'b1010_0100,
_3 = 8'b1011_0000, _4 = 8'b1001_1001, _5 = 8'b1001_0010,
_6 = 8'b1000_0010, _7 = 8'b1111_1000, _8 = 8'b1000_0000,
_9 = 8'b1001_0000;
/***************************************/
reg [7:0]rHunthu_SMG_Data;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
rHunthu_SMG_Data <= 8'b1111_1111;
end
else
case( Hunthu_Data )
4'd0 : rHunthu_SMG_Data <= _0;
4'd1 : rHunthu_SMG_Data <= _1;
4'd2 : rHunthu_SMG_Data<= _2;
4'd3 : rHunthu_SMG_Data <= _3;
4'd4 : rHunthu_SMG_Data <= _4;
4'd5 : rHunthu_SMG_Data <= _5;
4'd6 : rHunthu_SMG_Data<= _6;
4'd7 : rHunthu_SMG_Data<= _7;
4'd8 : rHunthu_SMG_Data<= _8;
4'd9 : rHunthu_SMG_Data <= _9;
endcase
/***************************************/
/***************************************/
reg [7:0]rTenthu_SMG_Data;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
rTenthu_SMG_Data <= 8'b1111_1111;
end
else
case( Tenthu_Data )
4'd0 : rTenthu_SMG_Data <= _0;
4'd1 : rTenthu_SMG_Data <= _1;
4'd2 : rTenthu_SMG_Data<= _2;
4'd3 : rTenthu_SMG_Data <= _3;
4'd4 : rTenthu_SMG_Data <= _4;
4'd5 : rTenthu_SMG_Data <= _5;
4'd6 : rTenthu_SMG_Data<= _6;
4'd7 : rTenthu_SMG_Data<= _7;
4'd8 : rTenthu_SMG_Data<= _8;
4'd9 : rTenthu_SMG_Data <= _9;
endcase
/***************************************/
/***************************************/
reg [7:0]rThu_SMG_Data;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
rThu_SMG_Data <= 8'b1111_1111;
end
else
case( Thu_Data )
4'd0 : rThu_SMG_Data <= _0;
4'd1 : rThu_SMG_Data <= _1;
4'd2 : rThu_SMG_Data<= _2;
4'd3 : rThu_SMG_Data <= _3;
4'd4 : rThu_SMG_Data <= _4;
4'd5 : rThu_SMG_Data <= _5;
4'd6 : rThu_SMG_Data<= _6;
4'd7 : rThu_SMG_Data<= _7;
4'd8 : rThu_SMG_Data<= _8;
4'd9 : rThu_SMG_Data <= _9;
endcase
/***************************************/
/***************************************/
reg [7:0]rHun_SMG_Data;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
rHun_SMG_Data <= 8'b1111_1111;
end
else
case( Hun_Data )
4'd0 : rHun_SMG_Data <= _0;
4'd1 : rHun_SMG_Data <= _1;
4'd2 : rHun_SMG_Data<= _2;
4'd3 : rHun_SMG_Data <= _3;
4'd4 : rHun_SMG_Data <= _4;
4'd5 : rHun_SMG_Data <= _5;
4'd6 : rHun_SMG_Data<= _6;
4'd7 : rHun_SMG_Data<= _7;
4'd8 : rHun_SMG_Data<= _8;
4'd9 : rHun_SMG_Data <= _9;
endcase
/***************************************/
reg [7:0]rTen_SMG_Data;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
rTen_SMG_Data <= 8'b1111_1111;
end
else
case( Ten_Data )
4'd0 : rTen_SMG_Data <= _0;
4'd1 : rTen_SMG_Data <= _1;
4'd2 : rTen_SMG_Data <= _2;
4'd3 : rTen_SMG_Data <= _3;
4'd4 : rTen_SMG_Data <= _4;
4'd5 : rTen_SMG_Data <= _5;
4'd6 : rTen_SMG_Data <= _6;
4'd7 : rTen_SMG_Data <= _7;
4'd8 : rTen_SMG_Data <= _8;
4'd9 : rTen_SMG_Data <= _9;
endcase
/***************************************/
reg [7:0]rOne_SMG_Data;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
rOne_SMG_Data <= 8'b1111_1111;
end
else
case( One_Data )
4'd0 : rOne_SMG_Data <= _0;
4'd1 : rOne_SMG_Data <= _1;
4'd2 : rOne_SMG_Data <= _2;
4'd3 : rOne_SMG_Data <= _3;
4'd4 : rOne_SMG_Data <= _4;
4'd5 : rOne_SMG_Data <= _5;
4'd6 : rOne_SMG_Data <= _6;
4'd7 : rOne_SMG_Data <= _7;
4'd8 : rOne_SMG_Data <= _8;
4'd9 : rOne_SMG_Data <= _9;
endcase
/***************************************/
assign Hunthu_SMG_Data = rHunthu_SMG_Data;
assign Thu_SMG_Data = rThu_SMG_Data;
assign Tenthu_SMG_Data = rTenthu_SMG_Data;
assign Hun_SMG_Data = rHun_SMG_Data;
assign Ten_SMG_Data = rTen_SMG_Data;
assign One_SMG_Data = rOne_SMG_Data;
/***************************************/
endmodule

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smg_scan_module.v

module smg_scan_module
(
CLK, RSTn,
Hunthu_SMG_Data, Tenthu_SMG_Data,Thu_SMG_Data, Hun_SMG_Data,Ten_SMG_Data, One_SMG_Data,
Row_Scan_Sig, Column_Scan_Sig
);
input CLK;
input RSTn;
input [7:0] Hunthu_SMG_Data;
input [7:0]Tenthu_SMG_Data;
input [7:0]Thu_SMG_Data;
input [7:0]Hun_SMG_Data;
input [7:0]Ten_SMG_Data;
input [7:0]One_SMG_Data;
output [7:0]Row_Scan_Sig;
output [5:0]Column_Scan_Sig;
/*****************************/
row_scan_module U1
(
.CLK( CLK ),
.RSTn( RSTn ),
.Hunthu_SMG_Data( Hunthu_SMG_Data ), // input - from top
.Tenthu_SMG_Data( Tenthu_SMG_Data ), // input - from top
.Thu_SMG_Data( Thu_SMG_Data ), // input - from top
.Hun_SMG_Data( Hun_SMG_Data ), // input - from top
.Ten_SMG_Data( Ten_SMG_Data ), // input - from top
.One_SMG_Data( One_SMG_Data ), // input - from top
.Row_Scan_Sig( Row_Scan_Sig ) // output - to top
);
column_scan_module U2
(
.CLK( CLK ),
.RSTn( RSTn ),
.Column_Scan_Sig( Column_Scan_Sig ) // output - to top
);
/********************************/
endmodule