[社招-成都] VeriSilicon（成都）招聘ASIC Design/DV/Video IP Design/算法等职位

2016-12-2 13:17:00 2868

本帖最后由冰之吻永恒于 2016-12-2 11:03 编辑

VeriSilicon（成都）社会招聘强势来袭，欢迎投递简历至邮箱：yujuan.li@verisilicon.com

Senior/Staff ASICDesign Engineer

Designtop-of-the-line ISP or graphics processors, including specification,architecture, micro-architecture, implementation (using Verilog), andverification

Requirement:

1. Masterdegree or above in CS, EE

2. 3+ yearshands-on experience

3. Programmingskills in Verilog HDL

4. Must be familiarwith all stages of the ASIC design flow (including specification, architecture,and design

implementation)

5. Highlymotivated and skillful at solving difficult technical problems

6. Knowledgeof computer graphics and low-power design techniques a plus

7. Experienceof ISP or GPU design or compression design a plus.

Senior Design Verification Engineer

Responsibility:

1. Plan the verification of complex digital design blocks by fullyunderstanding the design specification and interacting with design teams toidentify important verification scenarios

2. Create constrained-random verification environment using python,verilog (or system verilog)

3. Develop functional/performance test cases

4. Identify and write all types of coverage measures for stimulus andcorner-cases

5. Debug tests to deliver functional correct blocks

6. Disciplined issue reporting, bug tracking and communication ofdesign risks & status

BasicQualifications :

1. MS degree in Electrical Engineering or equivalent practicalexperience

2. Experience in the verification of designs such as GPUs, CPUs,networking or peripheral controllers

3. Experienced with the full verification cycle

4. Strong knowledge of system Verilog and C++

5. Experience with scripting language(Python, Perl preferred)

6. Strong communicator and team player

7. Strong problem solver

Preferred Qualifications :

1. At least 2 years of design experience on complicated blocks

2. Experience with profiling, performance or power simulation

3. Familiar with FPGA flow and comfortable with lab debugging

Senior/Staff Engineer of Video IP Design

Responsibilities:

1. Play an important role in defining video IP spec and devisingVideo IP architecture

2. Develop challenging modules including module spec definition,macro architecture design, RTL coding, C coding, simulation and synthesis

3. Carry out IP level verification or IP blocksintegration/implementation

4. Help junior engineers to solve technical issues

5. Support customers regarding Video IP application

Requirements:

1. Bachelor degree or above in EE

2. 5+ years of work experience in related areas

3. Good knowledge of some of the following general IP: H.264, H.265,MPEG, JPEG, AVS, AVS+ decoder & encoder and so on

4. Skilled in the field of digital circuit design, whole digitaldesign flow and EDA tools

5. Skilled in some of the following disciplines: RTL coding, Ccoding, Catapult C coding, simulation, synthesis/DFT/STA. Knowledge aboutcatapult C design flow is a plus

6. Key member in at least one mature silicon proven video IP

7. Fluent in both English and Chinese

8. Self motivated, good communication skill and team work spirit

Video Codec Algorithm Engineer

Responsibility:

1. Video codec algorithm research and optimization;

2. C-Model design and realization;

3. Develop and test the video codec control software;

4. Assistant the hardware engineers to optimize the performance ofhardware modules and area;

5. Help hardware and system engineers for system verification tosolve the related technical issues

6. Resolve customer multimedia system software problems on Android orLinux OS, that use company’s video codec IP.

Requirements:

1. Over 5-years of related working experience in video codecalgorithm research fields, or video multimedia software.

2. MS, PHD , in EE , CS or related IT technology fields;

3. Skilled in the field of digital video codec, special on H.264 orH.265, expert in C/C++ design, better on embedded software field , familiarwith Linux or Android multimedia frame work, OMX or Y4L2;

4. Some knowledge on hardware design and optimization is better;

5. Good Mandarin and English communication skills;

6. Good team work and passion in high pressure.

Application Engineer

Job Description

You will participatein design and verification of various IP developments in order to beacquainting with sophisticated design flows and products.

You will own one ormore functional blocks (or IPs) and your role will include (when candidateofficially become A.E., they can focus on bold items)

1. Functionalverification

2. Performancevalidation

3. Debugfailures in simulation to root-cause problems

4. Closelywork with architecture/design team of the block for test/bench development,execution and debug

5. Addressissues reported by customer during IP integration

6. Issuestracking

Requirements:

1. MS/BS EE

2. Good command of written and spoken English.

3. Good communication skill

4. In-depth knowledge and hands-on experience in ASIC design flowincluding

-RTL coding / reading

-Strong background in SOC verification methodology and test benchdevelopment using verilog, System verilog, UVM

and c++.

-Synthesis

5. Knowledge of unix/linux environment and scripting(shell/perl/python)

6. Familiar with FPGA mapping flow. comfortable with FPGA or Silicondebugging.

7. Self-motivated team player able to thrive in a fast-speedengineering environment.

8. Flexibility for Overseas Traveling

2D/3D Graphic System Verification

Responsibilities:

Thecandidate will be responsible for GPU system level verification, includingdeveloping system test cases, writing OpenGL applications and debuggingc-model.

Requirements:

1. Master degree in CS or EE.

2. Excellent in mathematics and well understanding of 3D Graphicstheory and GPU pipeline;

3. Good understanding in Computer Architecture. Knowing Logic designis a plus.

4. Strong programming skills in C/C++. Having Python experienceis a plus.

5. Familiar with D3D or OpenGL standard, and be proficient incorresponding driver development is a plus.

6. Good written and spoken English;

7. Good communication skills and able to work both independently.

Software Development Engineer

Description:

VerisiliconOpenCL/OpenGL driver group is designing and implementing OpenCL/OpenGL driverto expose best performance and 3D render effect of chip designed by Hardwaregroup. We are looking for talented people who are interested in parallel computing/3Drender and driver development.

Requirements:

1. Study GPU architecture and new compute features;
2. Study standard OpenCL specification;
3. Study standard OpenGL/OpenGLES specification;
4. Develop sample code that could benefit from Versilicon hardware specialdesignment;
5. Develop OpenCL/OpenGL/OpenES driver, include discuss with hardware team tomaximize Verisilicon chip
performance and render quality;

Minimum Qualifications:

1. New graduation or2Y+ working experience;

2. MS Degree in relevant discipline (CS, EE, Math);
3. Strong programming skills in C or C++;
4. Background in computer architecture, parallel processing, signal processingand/or high performance

computing would bepreferred;

5. Background in 3D model/render, computer graphics, game engine, etc, would be preferred;
6. Experience of working with a large code base with C/C++;
7. Good communication and team work;
8. General English skill (read, write);

芯原微电子（成都）有限公司诚邀您的加入！！！

公司地址：天府软件园C区10栋23楼；

简历投递邮箱：yujuan.li@verisilicon.com

芯原股份有限公司（芯原）是一家芯片设计平台即服务（SiliconPlatform as a Service，SiPaaSTM）提供商，为包含移动互联设备、数据中心、物联网（IoT）、可穿戴设备、智能家居和汽车电子等多种终端市场在内的各种广泛应用提供以IP为中心的、基于平台的芯片定制服务和一站式端到端的半导体设计服务。

芯原成立于2001年，总部位于中国上海，目前在全球已有超过600名员工。芯原在中国、美国和芬兰共设有6个设计研发中心，并在全球共设有9个销售和客户支持办事处。