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entity led_water is
port( clk : in std_logic; led : out std_logic_vector(7 downto 0) ); end led_water; architecture Behavioral of led_water is signal clk1 : std_logic; --建立中间时钟信号 begin process(clk) --进程1 对时钟信号进行N分频 variable count : natural range 0 to 40000000 := 0; variable count1 : std_logic := '0'; begin if(clk'event and clk = '1') then --如果clk上升沿到来 if(count = 40000000) then count := 0; clk1 <= clk1; else count := count + 1; end if; end if; end process; process(clk1) --对分频信号进行计数,进而控制LED灯亮灭 variable count2 : integer range 0 to 8 := 0; begin if(clk1'event and clk1 = '1') then count2 := count2 + 1; if (count2 = 8) then count2 := 0; end if; end if; case count2 is when 0 => led <= "00000001"; when 1 => led <= "00000010"; when 2 => led <= "00000100"; when 3 => led <= "00001000"; when 4 => led <= "00010000"; when 5 => led <= "00100000"; when 6 => led <= "01000000"; when 7 => led <= "10000000"; when others => led <= (others => 'Z'); end case; end process; end Behavioral; |
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回帖奖励 +1 分积分
现在基本上都用verilog
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