modelsim仿真是出现warning，不去波形，求解答

# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /svpwm_2_vhd_tst/i1/b2v_inst9
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /svpwm_2_vhd_tst/i1/b2v_inst9
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /svpwm_2_vhd_tst/i1/b2v_inst9
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /svpwm_2_vhd_tst/i1/b2v_inst8
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
#    Time: 0 ps  Iteration: 0  Instance: /svpwm_2_vhd_tst/i1/b2v_inst8
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /svpwm_2_vhd_tst/i1/b2v_inst8
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
#    Time: 0 ps  Iteration: 0  Instance: /svpwm_2_vhd_tst/i1/b2v_inst8
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /svpwm_2_vhd_tst/i1/b2v_inst8
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
#    Time: 0 ps  Iteration: 0  Instance: /svpwm_2_vhd_tst/i1/b2v_inst8


网上查到说是信号没有赋初值，可是我已经明明赋了，而且我测试文件也编写输入了。
它警告都是说8,9模块，是我8,9模块错了吗？
================第八模块===========================
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity vector_time is
Port(Ts: in INTEGER;
     Ud: in INTEGER;
     Uab: in std_logic_vector(7 downto 0);
     Ubc: in std_logic_vector(7 downto 0);
     Uca: in std_logic_vector(7 downto 0);
     N:in INTEGER;
     Tx: out INTEGER;
     Ty: out INTEGER);
end vector_time;

architecture Behavioral of vector_time is
signal x, y : INTEGER:=0;
begin
process(Uab,Ubc,Uca,N)
variable temp_1:integer range 0 to 255;
variable temp_2:integer range 0 to 255;
variable temp_3:integer range 0 to 255;
begin
temp_1 := conv_integer(Uab);
temp_2 := conv_integer(Ubc);
temp_3 := conv_integer(Uca);
case N is
when 1=>x<=temp_2;y<=temp_1;
when 2=>x<=-temp_1;y<=-temp_3;
when 3=>x<=temp_3;y<=temp_2;
when 4=>x<=-temp_2;y<=-temp_1;
when 5=>x<=temp_1;y<=temp_3;
when 6=>x<=-temp_3;y<=-temp_2;
when others=>null;
end case;
end process;
Tx<=x*Ts/Ud;
Ty<=y*Ts/Ud;
end Behavioral;
============================第九模块==========================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sector is
Port(Uab:in std_logic_vector(7 downto 0);
     Ubc:in std_logic_vector(7 downto 0);
     Uca:in std_logic_vector(7 downto 0);
     N:out INTEGER );
end sector;

architecture Behavioral of sector is
  signal x:STD_LOGIC_VECTOR(2 downto 0):="000";
begin
x(2)<='1' when Uab>=0 else'0';
x(1)<='1' when Ubc>=0 else'0';
x(0)<='1' when Uca>=0 else'0';
process(x)
begin
case x is
when"110"=>N<=1;
when"010"=>N<=2;
when"011"=>N<=3;
when"001"=>N<=4;
when"101"=>N<=5;
when"100"=>N<=6;
when others=>null;
end case;
end process;
end Behavioral;

求大神解答