quartus编译出现的warning，求助！急

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENtiTY freq IS
PORT
(
clk, xclk : IN STD_LOGIC;
rst :IN STD_LOGIC;
ceen:out std_logic;
led1,led2,led3,led4:out std_logic_vector(6 DOWNTO 0);
ge,shi,bai,qian :OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END freq;
ARCHITECTURE behav OF freq IS
SIGNAL count0 : STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
SIGNAL count1 : STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
SIGNAL count2 : STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
SIGNAL count3 : STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
SIGNAL num : STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
SIGNAL clr,en,c0,c1,c2 : STD_LOGIC;
SIGNAL NO1,NO2,NO3,NO4:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
END behav;