quartusII 做频率计输出有误差 怎么调小 用下面的程序现在输出是1分频 错的离谱

0_5hz
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity fenpin is
port(clk: in std_logic;clk0_5Hz:out std_logic);
end fenpin;

architecture segled of fenpin is
begin
p1:process(clk)
variable count:integer range 0 to 6249999;
begin
    if clk'event and clk='1' then
    if count<=3124999 then
      clk0_5Hz<='0';
      count:=count+1;
      elsif count>3124999 and count<=6249999 then
              clk0_5Hz<='1';
              count:=count+1;
          else count:=0;
        end if;
        end if;
end process p1;
END ARCHITECTURE SEGLED;

1hz分频计程序
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity fenpin1 is
port(clk: in std_logic;clk1Hz:out std_logic);
end fenpin1;

architecture segled of fenpin1 is
begin
p1:process(clk)
variable count:integer range 0 to 49999999;
begin
    if clk'event and clk='1' then
    if count<=24999999 then
      clk1Hz<='0';
      count:=count+1;
      elsif count>24999999 and count<=49999999 then
              clk1Hz<='1';
              count:=count+1;
          else count:=0;
        end if;
        end if;
end process p1;
END ARCHITECTURE SEGLED;