谁有关于TMS320F240这个的寄存器的详细说明

TMS320F240的寄存器配置文件，在初始化系统是实用

/****************************************************************************************/
/* File Name:    C240.h                                                              */
/* Originator:    Texas Instruments                                                       */
/*                                                                                      */
/* Description:    F240 Header file containing all peripheral register                     */
/*                declarations as well as other useful definitions.                       */
/*                                                                                      */
/*                                                                                      */
/*                                                                                      */
/****************************************************************************************/
/****************************************************************************************/
/* On Chip Periperal Register Definitions (All registers mapped into data               */
/* space unless otherwise noted)                                                        */
/****************************************************************************************/

/*C2xx Core Registers   */

#define IMR        (volatile unsigned int *)0x0004        /*interrupt Mask Register  */
#define GREG    (volatile unsigned int *)0x0005        /*Global memory allocation Register*/
#define IFR        (volatile unsigned int *)0x0006        /*Interrupt Flag Register*/

/*System Module Registers   */

#define SYSCR    (volatile unsigned int *)0x07018    /*System Module Control Register*/
#define SYSSR    (volatile unsigned int *)0x0701A    /*System Module Status Register*/
#define SYSIVR    (volatile unsigned int *)0x0701E    /*System Interrupt Vector Register*/

/*Watch-Dog(WD) / Real Time Int(RTI) / Phase Lock Loop(PLL) Registers     */

#define RTICNTR    (volatile unsigned int *)0x07021    /*RTI Counter Register*/
#define WDCNTR     (volatile unsigned int *)0x07023    /*WD Counter Register*/
#define WDKEY    (volatile unsigned int *)0x07025    /*WD Key Register*/
#define RTICR    (volatile unsigned int *)0x07027    /*RTI Control Register*/
#define WDCR    (volatile unsigned int *)0x07029           /*WD Control Register*/
#define CKCR0    (volatile unsigned int *)0x0702B    /*Clock Control Register 0*/
#define CKCR1    (volatile unsigned int *)0x0702D    /*Clock Control Register 1*/

/*Analog-to-Digital Converter(ADC) registers     */

#define ADCTRL1    (volatile unsigned int *)0x07032    /*ADC Control Register 1*/
#define ADCTRL2    (volatile unsigned int *)0x07034    /*ADC Control Register 2*/
#define ADCFIFO1    (volatile unsigned int *)0x07036    /*ADC Data Register FIFO1*/
#define ADCFIFO2    (volatile unsigned int *)0x07038    /*ADC Data Register FIFO2*/

/*Serial Peripheral Interface (SPI) Registers       */

#define SPICCR    (volatile unsigned int *)0x07040    /*SPI Configuration Control Register*/
#define SPICTL    (volatile unsigned int *)0x07041    /*SPI Operation Control Register*/
#define SPISTS    (volatile unsigned int *)0x07042    /*SPI Status Register*/
#define SPIBRR    (volatile unsigned int *)0x07044    /*SPI Baud Rate Register*/
#define SPIEMU    (volatile unsigned int *)0x07046    /*SPI Emulation buffer Register*/
#define SPIBUF    (volatile unsigned int *)0x07047    /*SPI Serial Input Buffer Register*/
#define SPIDAT    (volatile unsigned int *)0x07049    /*SPI Serial Data Register*/
#define SPIPC1    (volatile unsigned int *)0x0704D    /*SPI Port Control Register 1*/
#define SPIPC2    (volatile unsigned int *)0x0704E    /*SPI Port Control Register 2*/
#define SPIPRI    (volatile unsigned int *)0x0704F    /*SPI Priority control Register*/

/*Serial Communications Interface (SCI) Registers    */

#define SCICCR    (volatile unsigned int *)0x07050    /*SCI Communication Control Register*/
#define SCICTL1    (volatile unsigned int *)0x07051    /*SCI Control Register 1*/
#define SCIHBAUD    (volatile unsigned int *)0x07052    /*SCI Baud Select register, high bits*/
#define SCILBAUD    (volatile unsigned int *)0x07053    /*SCI Baud Select register, high bits*/
#define SCICTL2    (volatile unsigned int *)0x07054    /*SCI Control Register 2*/
#define SCIRXST    (volatile unsigned int *)0x07055    /*SCI Receive Status Register*/
#define SCIRXEMU    (volatile unsigned int *)0x07056    /*SCI Emulation data buffer Register*/
#define SCIRXBUF    (volatile unsigned int *)0x07057    /*SCI Receiver data buffer Register*/
#define SCITXBUF    (volatile unsigned int *)0x07059    /*SCI Transmit data buffer Register*/
#define SCIPC2    (volatile unsigned int *)0x0705E    /*SCI Port Control Register 2*/
#define SCIPRI     (volatile unsigned int *)0x0705F    /*SCI Priority Control Register*/

/*External Interrupt Registers      */

#define XINT1CR    (volatile unsigned int *)0x07070    /*Interrupt 1 Control Register*/
#define NMICR    (volatile unsigned int *)0x07072    /*Non-maskable Interrupt Control Register*/
#define XINT2CR    (volatile unsigned int *)0x07078    /*Interrupt 2 Control Register*/
#define XINT3CR    (volatile unsigned int *)0x0707A    /*Interrupt 3 Control Register*/

/*Digital I/O      */

#define OCRA    (volatile unsigned int *)0x07090    /*Output Control Reg A*/
#define OCRB    (volatile unsigned int *)0x07092    /*Output Control Reg B*/
#define PADATDIR    (volatile unsigned int *)0x07098    /*I/O port A Data & Direction reg.*/
#define PBDATDIR    (volatile unsigned int *)0x0709A    /*I/O port B Data & Direction reg.*/
#define PCDATDIR    (volatile unsigned int *)0x0709C    /*I/O port C Data & Direction reg.*/

/*General Purpose Timer Registers - Event Manager (EV)   */

#define GPTCON    (volatile unsigned int *)0x7400        /*General Purpose Timer Control Register*/
#define T1CNT    (volatile unsigned int *)0x7401        /*GP Timer 1 Counter Register*/
#define T1CMPR    (volatile unsigned int *)0x7402        /*GP Timer 1 Compare Register*/
#define T1PR    (volatile unsigned int *)0x7403        /*GP Timer 1 Period Register*/
#define T1CON    (volatile unsigned int *)0x7404        /*GP Timer 1 Control Register*/
#define T2CNT    (volatile unsigned int *)0x7405        /*GP Timer 2 Counter Register*/
#define T2CMPR    (volatile unsigned int *)0x7406        /*GP Timer 2 Compare Register*/
#define T2PR    (volatile unsigned int *)0x7407        /*GP Timer 2 Period Register*/
#define T2CON    (volatile unsigned int *)0x7408        /*GP Timer 2 Control Register*/
#define T3CNT    (volatile unsigned int *)0x7409        /*GP Timer 3 Counter Register*/
#define T3CMPR    (volatile unsigned int *)0x740A    /*GP Timer 3 Compare Register*/
#define T3PR    (volatile unsigned int *)0x740B    /*GP Timer 3 Period Register*/
#define T3CON    (volatile unsigned int *)0x740C    /*GP Timer 3 Control Register*/

/*Full & Simple Compare Unit Registers - Event Manager (EV)  */

#define COMCON    (volatile unsigned int *)0x7411        /*Compare Control Register*/
#define ACTR    (volatile unsigned int *)0x7413        /*Full Compare Action Control Register*/
#define SACTR    (volatile unsigned int *)0x7414        /*Simple Compare Action Control Register*/
#define DBTCON    (volatile unsigned int *)0x7415        /*Dead-band Timer Control Register*/
#define CMPR1    (volatile unsigned int *)0x7417        /*Full Compare Unit 1 Compare Register*/
#define CMPR2    (volatile unsigned int *)0x7418        /*Full Compare Unit 2 Compare Register*/
#define CMPR3    (volatile unsigned int *)0x7419        /*Full Compare Unit 3 Compare Register*/
#define SCMPR1    (volatile unsigned int *)0x741A    /*Simple Compare Unit 1 CompareRegister*/
#define SCMPR2    (volatile unsigned int *)0x741B    /*Simple Compare Unit 2 CompareRegister*/
#define SCMPR3    (volatile unsigned int *)0x741C    /*Simple Compare Unit 3 CompareRegister*/

/*Capture & QEP Registers - Event Manager (EV)   */

#define CAPCON    (volatile unsigned int *)0x7420        /*Capture Control Register*/
#define CAPFIFO    (volatile unsigned int *)0x7422        /*Capture FIFO Status Register*/
#define CAP1FIFO    (volatile unsigned int *)0x7423        /*Capture 1 Two-level deep FIFO Register*/
#define CAP2FIFO    (volatile unsigned int *)0x7424        /*Capture 2 Two-level deep FIFO Register*/
#define CAP3FIFO    (volatile unsigned int *)0x7425        /*Capture 3 Two-level deep FIFO Register*/
#define CAP4FIFO    (volatile unsigned int *)0x7426        /*Capture 4 Two-level deep FIFO Register*/

/*Interrupt Registers - Event Manager (EV)   */

#define EVIMRA    (volatile unsigned int *)0x742C    /*EV Interrupt Mask Register A*/
#define EVIMRB    (volatile unsigned int *)0x742D    /*EV Interrupt Mask Register B*/
#define EVIMRC     (volatile unsigned int *)0x742E    /*EV Interrupt Mask Register C*/
#define EVIFRA    (volatile unsigned int *)0x742F    /*EV Interrupt Flag Register A*/
#define EVIFRB    (volatile unsigned int *)0x7430        /*EV Interrupt Flag Register B*/
#define EVIFRC    (volatile unsigned int *)0x7431        /*EV Interrupt Flag Register C*/
#define EVIVRA    (volatile unsigned int *)0x7432        /*EV Interrupt Vector Register A*/
#define EVIVRB    (volatile unsigned int *)0x7433        /*EV Interrupt Vector Register B*/
#define EVIVRC     (volatile unsigned int *)0x7434        /*EV Interrupt Vector Register C*/

/*Wait State Generator Registers (mapped into I/O space)   */

#define WSGR    (volatile unsigned int *)0xFFFF    /*Wait State Generator Register*/