# PIN RESET
p Reset 0 # Release the reset pin
d 5000
p Reset 1 # Release the reset pin
# RESET
w 30 00 00 # Select register page 0
w 30 01 80 # I2C reset
d 5000
# DATA PATH
w 30 07 0A # Left DAC left channel, right DAC right channel
w 30 09 00 # I2S, 16-bit, continuous clock, no resync
w 30 1C C0 # Hysteresis is disabled
w 30 1F C0 # Hysteresis is disabled
w 30 25 C0 # DAC Power and Output Driver Control Register
w 30 2B 00 # Left-DAC Digital Volume Control Register
w 30 2C 00 # Right-DAC Digital Volume Control Register
# OUTPUT VOLUME OFFSETS
w 30 33 5D # HPLOUT mute + power down (weakly driven to common mode)
w 30 41 5D # HPROUT mute + power down (weakly driven to common mode)
w 30 3A 5D # HPLCOM mute + power down (weakly driven to common mode)
w 30 48 5D # HPRCOM mute + power down (weakly driven to common mode)
w 30 2F 80 # DAC_L1 is routed to HPLOUT, volume = 0 dB
w 30 36 80 # DAC_L1 is routed to HPLCOM, volume = 0 dB
w 30 40 80 # DAC_R1 is routed to HPROUT, volume = 0 dB
w 30 47 80 # DAC_R1 is routed to HPRCOM, volume = 0 dB
w 30 32 80 ## DAC_R1 is routed to HPLOUT, volume = 0 dB
w 30 39 80 ## DAC_R1 is routed to HPLCOM, volume = 0 dB
w 30 3D 80 ## DAC_L1 is routed to HPROUT, volume = 0 dB
w 30 44 80 ## DAC_L1 is routed to HPRCOM, volume = 0 dB
w 30 52 80 # DAC_L1 is routed to LEFT_LOP/M, volume = 0 dB
w 30 5C 80 # DAC_R1 is routed to RIGHT_LOP/M, volume = 0 dB
w 30 55 80 ## DAC_R1 is routed to LEFT_LOP/M, volume = 0 dB
w 30 59 80 ## DAC_L1 is routed to RIGHT_LOP/M, volume = 0 dB
w 30 56 09 # Register 86: LEFT_LOP/M Output Level Control Register
w 30 5D 09 # Register 93: RIGHT_LOP/M Output Level Control Register