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donatello1996

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[经验]

【Vision Board创客营连载体验】RA8D1-Vision Board 驱动正点原子7寸RGB液晶屏

      RA8D1-Vision Board开发板带了跟正点原子一样的RGB液晶屏接口，因此是可以接原子的屏的：
1.jpg

RASC配置RGB565十六位色接口（引脚为RGB666十八位色，但是屏幕只用到了前十六位，也就是DATA0~DATA15）：
2.jpg

配置TCON0 TCON1 TCON3分别为HSYNC VSYNC DE：
3.jpg

由于我之前已经使用RA6M3接过原子的4.3寸屏，所以很多参数可以照搬，但有部分参数是需要参考原子的例程：
Output|timing|Horizontal total cycles        1165
Output|Timing|Horizontal active video cycles        1024
Output|Timing|Horizontal back porch cycles        140
Output|Timing|Horizontal sync signal cycles        1
Output|Timing|Horizontal sync signal polarity        Low active
Output|Timing|Vertical total lines        621
Output|Timing|Vertical active video lines        600
Output|Timing|Vertical back porch lines        20
Output|Timing|Vertical sync signal lines        1
Output|Timing|Vertical sync signal polarity        Low active
Output|Timing|Data Enable Signal Polarity        High active
Output|Timing|Sync edge        Falling edge
Output|Format|Color format        16bits RGB565
Output|Format|Color order        RGB
Output|Format|Endian        Little endian
4.jpg

由于原子的7寸屏是1024*600的分辨率，RA8D1芯片内部SRAM是不够存放显存缓存的，必须要放在外部的SDRAM：
Input|Graphics Layer 1|Framebuffer|Framebuffer name        fb_background
Input|Graphics Layer 1|Framebuffer|Section for framebuffer allocation        .sdram

TCON功能脚和HSYNC VSYNC等控制引脚也没有一一对应关系，都是通过分配实现的：
TCON|Hsync pin select        LCD_TCON1
TCON|Vsync pin select        LCD_TCON0
TCON|Data enable (DE) pin select        LCD_TCON3
TCON|Panel clock source        Internal clock (GLCDCLK)
TCON|Panel clock division ratio        1/8

SDRAM配置则直接照搬RTT工程即可：
5.jpg
显示屏驱动代码：
  1. #define LCD_WIDTH           1024
  3. #define LCD_HEIGHT          600
  7. uint16_t *lcd_current_working_buffer = (uint16_t *) &fb_background[0];
  11. void ra_bsp_lcd_clear(uint16_t color)
  13. {
  15.     for (uint32_t i = 0; i < (LCD_WIDTH * LCD_HEIGHT); i++)
  17.     {
  19.         lcd_current_working_buffer[i] = color;
  21.     }
  23. }
  27. void bsp_lcd_draw_pixel(uint32_t x, uint32_t y, uint16_t color)
  29. {
  31.         lcd_current_working_buffer[(y * LCD_WIDTH) + x] = color;
  33. }
  37. void lcd_fill_rectangle(uint16_t x_start, uint16_t y_start, uint16_t x_end, uint16_t y_end, uint16_t pixcolor)
  39. {
  41.     uint16_t cycle_y, x_offset = 0;
  45.     for (cycle_y = y_start; cycle_y <= y_end;)
  47.     {
  49.         for (x_offset = 0; x_start + x_offset <= x_end; x_offset++)
  51.         {
  53.             bsp_lcd_draw_pixel(x_start + x_offset, cycle_y, pixcolor);
  55.         }
  57.         cycle_y++;
  59.     }
  61. }

SDRAM驱动代码：
  1. #define BSP_PRV_SDRAM_SDIR_REF_TIMES           (2U)
  3. #define BSP_PRV_SDRAM_BUS_WIDTH                (0U)
  5. #define BSP_PRV_SDRAM_CONTINUOUS_ACCESSMODE    (1U)
  7. #define BSP_PRV_SDRAM_ENDIAN_MODE              (0U)
  9. #define BSP_PRV_SDRAM_MR_WB_SINGLE_LOC_ACC    (1U) /* MR.M9                : Single Location Access */
  11. #define BSP_PRV_SDRAM_MR_OP_MODE              (0U) /* MR.M8:M7             : Standard Operation */
  13. #define BSP_PRV_SDRAM_MR_BT_SEQUENCTIAL       (0U) /* MR.M3 Burst Type     : Sequential */
  15. #define BSP_PRV_SDRAM_MR_BURST_LENGTH         (0U) /* MR.M2:M0 Burst Length: 0(1 burst) */
  17. #define BSP_PRV_SDRAM_CL                       (3U)
  19. #define BSP_PRV_SDRAM_TRP                      (3U)
  21. #define BSP_PRV_SDRAM_TWR                      (2U)
  23. #define BSP_PRV_SDRAM_TRAS                     (6U)
  25. #define BSP_PRV_SDRAM_TRCD                     (3U)
  27. #define BSP_PRV_SDRAM_SDADR_ROW_ADDR_OFFSET    (9U)
  29. #define BSP_PRV_SDRAM_TRFC                     (8U)
  31. #define BSP_PRV_SDRAM_REF_CMD_INTERVAL         (937U)
  35. void bsp_sdram_init (void)
  37. {
  39.     /** Setting for SDRAM initialization sequence */
  41. #if (BSP_PRV_SDRAM_TRP < 3)
  43.     R_BUS->SDRAM.SDIR_b.PRC = 3U;
  45. #else
  47.     R_BUS->SDRAM.SDIR_b.PRC = BSP_PRV_SDRAM_TRP - 3U;
  49. #endif
  53.     while (R_BUS->SDRAM.SDSR)
  55.     {
  57.         /* According to h/w maual, need to confirm that all the status bits in SDSR are 0 before SDIR modification. */
  59.     }
  63.     R_BUS->SDRAM.SDIR_b.ARFC = BSP_PRV_SDRAM_SDIR_REF_TIMES;
  67.     while (R_BUS->SDRAM.SDSR)
  69.     {
  71.         /* According to h/w maual, need to confirm that all the status bits in SDSR are 0 before SDIR modification. */
  73.     }
  77. #if (BSP_PRV_SDRAM_TRFC < 3)
  79.     R_BUS->SDRAM.SDIR_b.ARFI = 0U;
  81. #else
  83.     R_BUS->SDRAM.SDIR_b.ARFI = BSP_PRV_SDRAM_TRFC - 3U;
  85. #endif
  89.     while (R_BUS->SDRAM.SDSR)
  91.     {
  93.         /* According to h/w maual, need to confirm that all the status bits in SDSR are 0 before SDICR modification. */
  95.     }
  99.     /** Start SDRAM initialization sequence.
  101.      * Following operation is automatically done when set SDICR.INIRQ bit.
  103.      * Perform a PRECHARGE ALL command and wait at least tRP time.
  105.      * Issue an AUTO REFRESH command and wait at least tRFC time.
  107.      * Issue an AUTO REFRESH command and wait at least tRFC time.
  109.      */
  111.     R_BUS->SDRAM.SDICR_b.INIRQ = 1U;
  113.     while (R_BUS->SDRAM.SDSR_b.INIST)
  115.     {
  117.         /* Wait the end of initialization sequence. */
  119.     }
  123.     /** Setting for SDRAM controller */
  125.     R_BUS->SDRAM.SDCCR_b.BSIZE  = BSP_PRV_SDRAM_BUS_WIDTH;             /* set SDRAM bus width */
  127.     R_BUS->SDRAM.SDAMOD_b.BE    = BSP_PRV_SDRAM_CONTINUOUS_ACCESSMODE; /* enable continuous access */
  129.     R_BUS->SDRAM.SDCMOD_b.EMODE = BSP_PRV_SDRAM_ENDIAN_MODE;           /* set endian mode for SDRAM address space */
  133.     while (R_BUS->SDRAM.SDSR)
  135.     {
  137.         /* According to h/w maual, need to confirm that all the status bits in SDSR are 0 before SDMOD modification. */
  139.     }
  143.     /** Using LMR command, program the mode register */
  145.     R_BUS->SDRAM.SDMOD = ((((uint16_t) (BSP_PRV_SDRAM_MR_WB_SINGLE_LOC_ACC << 9) |
  147.                             (uint16_t) (BSP_PRV_SDRAM_MR_OP_MODE << 7)) |
  149.                            (uint16_t) (BSP_PRV_SDRAM_CL << 4)) |
  151.                           (uint16_t) (BSP_PRV_SDRAM_MR_BT_SEQUENCTIAL << 3)) |
  153.                          (uint16_t) (BSP_PRV_SDRAM_MR_BURST_LENGTH << 0);
  157.     /** wait at least tMRD time */
  159.     while (R_BUS->SDRAM.SDSR_b.MRSST)
  161.     {
  163.         /* Wait until Mode Register setting done. */
  165.     }
  169.     /** Set timing parameters for SDRAM */
  171.     R_BUS->SDRAM.SDTR_b.RAS = BSP_PRV_SDRAM_TRAS - 1U; /* set ACTIVE-to-PRECHARGE command cycles*/
  173.     R_BUS->SDRAM.SDTR_b.RCD = BSP_PRV_SDRAM_TRCD - 1U; /* set ACTIVE to READ/WRITE delay cycles */
  175.     R_BUS->SDRAM.SDTR_b.RP  = BSP_PRV_SDRAM_TRP - 1U;  /* set PRECHARGE command period cycles */
  177.     R_BUS->SDRAM.SDTR_b.WR  = BSP_PRV_SDRAM_TWR - 1U;  /* set write recovery cycles */
  179.     R_BUS->SDRAM.SDTR_b.CL  = BSP_PRV_SDRAM_CL;        /* set SDRAM column latency cycles */
  183.     /** Set row address offset for target SDRAM */
  185.     R_BUS->SDRAM.SDADR_b.MXC = BSP_PRV_SDRAM_SDADR_ROW_ADDR_OFFSET - 8U;
  189.     R_BUS->SDRAM.SDRFCR_b.REFW = (uint16_t) (BSP_PRV_SDRAM_TRFC - 1U); /* set Auto-Refresh issuing cycle */
  191.     R_BUS->SDRAM.SDRFCR_b.RFC  = BSP_PRV_SDRAM_REF_CMD_INTERVAL - 1U;  /* set Auto-Refresh period */
  195.     /** Start Auto-refresh */
  197.     R_BUS->SDRAM.SDRFEN_b.RFEN = 1U;
  201.     /** Enable SDRAM access */
  203.     R_BUS->SDRAM.SDCCR_b.EXENB = 1U;
  205. }

显示效果：
微信图片_20240507204421.jpg

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