VHDL编程出现两个错误，第13行”);“和第33行”begin“，（已标红）怎么修改？

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity cehou2 is
port(a1,a2,a3,a4:in std_logic;--输入信号
     reset:in std_logic;--系统复位信号
     bzh:in std_logic_vector(7 downto 0);
     clko:out std_logic;
     clk:in std_logic;--系统时钟
     ch1,ch2,ch3,xint:out std_logic;
          );
end cehou2;
architecture behave of cehou2 is
signal counter7,counter11:std_logic_vector(11 downto 0);
signal counter9:std_logic_vector(2 downto O);
signal counter50:std_logicvector(3 downto 0);
signal counterO,counter1:std_logic_vector(7 downto 0);
signal counter2:stdAogic_vector(11 downto 0);
signal counter31,counter32,counter33,counter34,counter1O:std_logic_vector(11 downto 0);
signal counter41,counter42,counter43,counter44:std_logic_vector(11 downto 0);
signal chn:std_logic_vector(2 downto 0);
signal counter6,counter8:std_logic_vector(15 downto 0);
signal
width,width1,width2,width3,width4,width1m,width2m,width3m,width4m,width1mm,width2mm,width3mm,width4mm,width11,width22,width33,width44,acounter1,acounter2,acounter3,acounter4:
std_logic_vector(11 downto 0);
signal trig,tri,clk1,clk3,clk33,clk2,fz2,fz22,fz4:std_logic;
constant line:integer:=50;
signal widthm1,widthm2,top11,bot11,top11m,bot11m,wid1,wid2:std_logic_vector(10 downto 0);
signal widthm3,widthm4,top1,bot1,top2,bot2:std_logicvector(11 downto 0);

begin
widthm2<=bzh&"000";
widl<="000"&bzh;
wid2<="0000"&bzh(7 downto 1);