参考Xilinx官网 “35308 - 14.x Timing - Why is my clock modifying block (CMB) (MMCM, DCM, PLL, etc.) min delay larger than the max?” 的回答。
“CMBs can use feedback to deskew the clocks. The path that is used as the feedback is larger for maximum clock calculations and smaller for minimum clock calculations.
The clock going out of the CMB is being phase matched with these delays and that is how we accomplish the 'deskewing' effect. The phase matching is modeled by subtracting the delay of the feedback path from the clock path. Therefore, on a minimum clock path calculation you will see a smaller negative number than you will for the maximum clock path calculations. ”
举报
