In the example, we synchronize Timer 1 and Timer 2. Timer 1 is the master and starts from 0. Timer 2 is the slave and starts from 0xE7. The prescaler ratio is the same for both timers. Timer 2 stops when Timer 1 is disabled by writing ‘0 to the CEN bit in the TIM1_CR1 register: • Configure Timer 1 master mode to send its Output Compare 1 Reference (OC1REF) signal as trigger output (MMS=100 in the TIM1_CR2 register). 定时器主模式选择器：MMS
Bits 6:4 MMS[2:0]: Master mode selection
These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows:
000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.
001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register).
010: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.
011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO)
100: Compare - OC1REF signal is used as trigger output (TRGO)
101: Compare - OC2REF signal is used as trigger output (TRGO)
110: Compare - OC3REF signal is used as trigger output (TRGO)
111: Compare - OC4REF signal is used as trigger output (TRGO) • Configure the Timer 1 OC1REF waveform (TIM1_CCMR1 register). 定时器捕捉输入模式，这种T1的输出波形 • Configure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR register).
T2的主从控制寄存器，设置触发选择器，
T2设置为T1触发输入
• Configure Timer 2 in gated mode (SMS=101 in TIM2_SMCR register).
T2主从控制器，从模式选择器，选择T2为Gate模式
• Reset Timer 1 by writing ‘1 in UG bit (TIM1_EGR register).
• Reset Timer 2 by writing ‘1 in UG bit (TIM2_EGR register).
重置，T1,T2的更新位，
Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting).
• Initialize Timer 2 to 0xE7 by writing ‘0xE7’ in the timer 2 counter (TIM2_CNT).
初始化T2的计数器，
• Enable Timer 2 by writing ‘1 in the CEN bit (TIM2_CR1 register).
• Start Timer 1 by writing ‘1 in the CEN bit (TIM1_CR1 register).
• Stop Timer 1 by writing ‘0 in the CEN bit (TIM1_CR1 register).
In the example, we synchronize Timer 1 and Timer 2. Timer 1 is the master and starts from 0. Timer 2 is the slave and starts from 0xE7. The prescaler ratio is the same for both timers. Timer 2 stops when Timer 1 is disabled by writing ‘0 to the CEN bit in the TIM1_CR1 register: • Configure Timer 1 master mode to send its Output Compare 1 Reference (OC1REF) signal as trigger output (MMS=100 in the TIM1_CR2 register). 定时器主模式选择器：MMS
Bits 6:4 MMS[2:0]: Master mode selection
These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows:
000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.
001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register).
010: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.
011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO)
100: Compare - OC1REF signal is used as trigger output (TRGO)
101: Compare - OC2REF signal is used as trigger output (TRGO)
110: Compare - OC3REF signal is used as trigger output (TRGO)
111: Compare - OC4REF signal is used as trigger output (TRGO) • Configure the Timer 1 OC1REF waveform (TIM1_CCMR1 register). 定时器捕捉输入模式，这种T1的输出波形 • Configure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR register).
T2的主从控制寄存器，设置触发选择器，
T2设置为T1触发输入
• Configure Timer 2 in gated mode (SMS=101 in TIM2_SMCR register).
T2主从控制器，从模式选择器，选择T2为Gate模式
• Reset Timer 1 by writing ‘1 in UG bit (TIM1_EGR register).
• Reset Timer 2 by writing ‘1 in UG bit (TIM2_EGR register).
重置，T1,T2的更新位，
Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting).
• Initialize Timer 2 to 0xE7 by writing ‘0xE7’ in the timer 2 counter (TIM2_CNT).
初始化T2的计数器，
• Enable Timer 2 by writing ‘1 in the CEN bit (TIM2_CR1 register).
• Start Timer 1 by writing ‘1 in the CEN bit (TIM1_CR1 register).
• Stop Timer 1 by writing ‘0 in the CEN bit (TIM1_CR1 register).
举报
