FPGA 上电问题

这是非常基本的问题，我举例说明一下，我常用的是Xilinx的7系列FPGA，它有一个PUDC_B配置管脚，只需要将它进行上拉即可取消内部上拉，这样在程序加载过程IO就会是默认高阻态。原资料如下描述：
PUDC_B Multi-function Input
Pull-Up During Configuration (bar)
PUDC_B input enables internal pull-up resistors on the
SelectIO pins after power-up and during configuration
(active Low).
• When PUDC_B is Low, internal pull-up resistors are
enabled on each SelectIO pin.
• When PUDC_B is High, internal pull-up resistors are
disabled on each SelectIO pin.
PUDC_B must be tied either directly (or through a 1KΩ or
less resistor) to VCCO_14 or GND.
Do not allow this pin to float before and during
configuration.