ad5432不受控制，vhdl程序如下所示，请问是芯片还是程序的问题
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
en
tity ad5432_driver is
port(
clk : in std_logic;
rst : in std_logic;
din : in std_logic_vector(9 downto 0);
sclk : out std_logic;
sync : out std_logic;
sdin : out std_logic
);
end entity ad5432_driver;
architecture one of ad5432_driver is
signal clk_cnt : std_logic_vector(3 downto 0);
signal din_reg : std_logic_vector(15 downto 0);
signal sclk_reg : std_logic;
signal flag : std_logic;
type state is (
s0,
s1,
s2,
s3,
s4,
s5,
s6,
s7,
s8,
s9,
s10,
s11,
s12,
s13,
s14,
s15,
s16
);
signal c_st, n_st : state;
begin
process(clk, rst)
begin
if rst = '0' then
clk_cnt <= (others => '0');
elsif clk'event and clk = '1' then
clk_cnt <= clk_cnt + '1';
end if;
end process;
sclk_reg <= clk_cnt(2);
process(sclk_reg, rst, n_st)
begin
if rst = '0' then
c_st <= s0;
elsif sclk_reg'event and sclk_reg = '1' then
c_st <= n_st;
end if;
end process;
process(c_st)
begin
case c_st is
when s0 => n_st <= s1;
when s1 => n_st <= s2; when s2 => n_st <= s3;
when s3 => n_st <= s4;
when s4 => n_st <= s5;
when s5 => n_st <= s6;
when s6 => n_st <= s7;
when s7 => n_st <= s8;
when s8 => n_st <= s9;
when s9 => n_st <= s10;
when s10 => n_st <= s11;
when s11 => n_st <= s12;
when s12 => n_st <= s13;
when s13 => n_st <= s14;
when s14 => n_st <= s15;
when s15 => n_st <= s16;
when s16 => n_st <= s0;
when others => n_st <= s0;
end case;
end process;
process(sclk_reg, rst, din, n_st)
begin
if rst = '0' then
din_reg <= "0000000000000011";
sync <= '1';
elsif sclk_reg'event and sclk_reg = '1' then
case n_st is
when s0 => din_reg <= "1001" & din & "11"; sync <= '1';
when s1 => sdin <= din_reg(15); sync <= '0';
when s2 => sdin <= din_reg(14); sync <= '0';
when s3 => sdin <= din_reg(13); sync <= '0';
when s4 => sdin <= din_reg(12); sync <= '0';
when s5 => sdin <= din_reg(11); sync <= '0';
when s6 => sdin <= din_reg(10); sync <= '0';
when s7 => sdin <= din_reg(9); sync <= '0';
when s8 => sdin <= din_reg(8); sync <= '0';
when s9 => sdin <= din_reg(7); sync <= '0';
when s10 => sdin <= din_reg(6); sync <= '0';
when s11 => sdin <= din_reg(5); sync <= '0';
when s12 => sdin <= din_reg(4); sync <= '0';
when s13 => sdin <= din_reg(3); sync <= '0';
when s14 => sdin <= din_reg(2); sync <= '0';
when s15 => sdin <= din_reg(1); sync <= '0';
when s16 => sdin <= din_reg(0); sync <= '0';
when others => din_reg <= "1001000000000011"; sync <= '1';
end case;
end if;
end process;
-- process(sclk_reg, rst, din, n_st)
-- begin
-- if rst = '0' then
-- sdin <= '0'; sync <= '1'; flag <= '0';
-- elsif sclk_reg'event and sclk_reg = '1' then
-- case n_st is
-- when s0 => sdin <= '0'; sync <= '1'; flag <= '0';
-- when s1 => sdin <= '1'; sync <= '0'; flag <= '1';
-- when s2 => sdin <= '0'; sync <= '0'; flag <= '1';
-- when s3 => sdin <= '0'; sync <= '0'; flag <= '1';
-- when s4 => sdin <= '1'; sync <= '0'; flag <= '1';
-- when s5 => sdin <= din(9); sync <= '0'; flag <= '1';
-- when s6 => sdin <= din(8); sync <= '0'; flag <= '1';
-- when s7 => sdin <= din(7); sync <= '0'; flag <= '1';
-- when s8 => sdin <= din(6); sync <= '0'; flag <= '1';
-- when s9 => sdin <= din(5); sync <= '0'; flag <= '1';
-- when s10 => sdin <= din(4); sync <= '0'; flag <= '1';
-- when s11 => sdin <= din(3); sync <= '0'; flag <= '1';
-- when s12 => sdin <= din(2); sync <= '0'; flag <= '1';
-- when s13 => sdin <= din(1); sync <= '0'; flag <= '1';
-- when s14 => sdin <= din(0); sync <= '0'; flag <= '1';
-- when s15 => sdin <= '0'; sync <= '0'; flag <= '1';
-- when s16 => sdin <= '0'; sync <= '0'; flag <= '1';
-- when others => sdin <= '0'; sync <= '1'; flag <= '0';
-- end case;
-- end if;
-- end process;
sclk <= sclk_reg;
end architecture one;
