请问tlv320aic3204是否支持单音配置？

调试环境：
我使用TMS320C5515 eZdsp USB Stick dsp单板，这个单板带有一个tlv320aic3204音频芯片；
目标：
我希望可以播放位速128kbps 音频采样大小 16位，单声道，音频采用级别8kHz，音频格式为pcm的音频文件：
参考：
  根据手册上的说明，要使用Mono方式，I2s需要使用DSP format.才有效，我将I2SSCTRL的FRMT置为1，这时就不能接收到音频信号，置为0则可以接收到音频信号。
问题：
请问tlv320aic3204 是否支持单音方式，能否提供参考配置，谢谢！
具体配置：
void aic3204_init_mono(void)
[
Uint16 regaddr;
SYS_EXBUSSEL = 0x6100;       // Enable I2C bus
USBSTK5515_I2C_init( );       // Initialize I2C
/* Configure AIC3204 */
AIC3204_rset( 0, 0 );       // Select page 0
AIC3204_rset( 1, 1 );       // Reset codec
USBSTK5515_wait( 500 );       // Wait
AIC3204_rset( 0, 1 );       // Point to page 1
AIC3204_rset( 1, 8 );       // Disabled weak connection of AVDD with DVDD
AIC3204_rset( 2, 1 );       // Enable Analog Blocks, use LDO power (is LDO power being used? If it is, then this register needs to be set correclty to use LDO).
/* PLL and Clocks config and Power Up  */
AIC3204_rset( 0, 0 );       // Select page 0
AIC3204_rset( 27, 0x4d );    // BCLK and WCLK is set as output from AIC3204(Master) 00: Audio Interface = dsp
AIC3204_rset( 28, 0x00 );    // Data ofset = 0
AIC3204_rset( 4, 3 );       // PLL setting: PLLCLK <- MCLK, CODEC_CLKIN <-PLL CLK
AIC3204_rset( 6, 8 );       // **PLL setting: J=8 (comment does not match)
AIC3204_rset( 7, 0x07 );    // PLL setting: HI_BYTE(D)
AIC3204_rset( 8, 0x80);    // PLL setting: LO_BYTE(D)
AIC3204_rset( 30, 0x80 );    // For 32 bit clocks per frame in Master mode ONLY (make sure that BCLK >= [ (# bits per channel) * 2 ]
                                 // BCLK=DAC_CLK/N =(12288000/8) = 1.536MHz = 32*fs
// For 8 KHz sampling
AIC3204_rset( 5, 0x91 );    // PLL setting: Power up PLL, P=1 and R=1
AIC3204_rset( 13, 0x01 );    // Hi_Byte(DOSR) for DOSR = 256 decimal or 0x01080 DAC oversamppling
AIC3204_rset( 14, 0x00 );    // Lo_Byte(DOSR) for DOSR = 256 decimal or 0x0100
AIC3204_rset( 20, 0x00 );    // AOSR for AOSR = 256 decimal or 0x0000 for decimation filters 1 to 6
AIC3204_rset( 11, 0x86 );    // Power up NDAC and set NDAC value to 3 (comments below differ from the values)
AIC3204_rset( 12, 0x88);    // Power up MDAC and set MDAC value to 8  (comments below differ from the values)
AIC3204_rset( 18, 0x88 );    // Power up NADC and set NADC value to 8  (comments below differ from the values)
AIC3204_rset( 19, 0x86 );    // Power up MADC and set MADC value to 6  (comments below differ from the values)
AIC3204_rset( 60, 0x19 );    // Power up PRB_P25 for beep generator Selects the ADC (recording) signal processing block
AIC3204_rset( 61, 0x01 );    // ADC Singal Processing Block PRB_R1  ADC Signal Processing Block Control Register
AIC3204_rset( 48, 0xff );    // Power up MADC and set MADC value to 6  (comments below differ from the values)
AIC3204_rset( 49, 0xff );    // Power up PRB_P25 for beep generator
/* DAC ROUTING and Power Up */
AIC3204_rset(  0, 0x01 );    // Select page 1
AIC3204_rset( 12, 0x08 );    // LDAC AFIR routed to HPL
AIC3204_rset( 13, 0x08 );    // RDAC AFIR routed to HPR &&&&&&&
AIC3204_rset( 14, 0x00 );    // Right Channel DAC reconstruction filter's negative terminal is not routed to LOL
AIC3204_rset( 15, 0x00 );    // Right Channel DAC reconstruction filter output is not routed to LOR
AIC3204_rset(  0, 0x00 );    // Select page 0
AIC3204_rset( 64, 0x02 );    // Left vol=right vol
AIC3204_rset( 65, 0x00 );    // Left DAC gain to 0dB VOL; Right tracks Left
AIC3204_rset( 66, 0x81 );    // right mute
AIC3204_rset( 63, 0xd4 );    // Power up left,right data paths and set channel
AIC3204_rset(  0, 0x01 );    // Select page 1
AIC3204_rset( 20, 0x69 );    // Soft Step, De-pop, 6 time constants, 6k ohm.
AIC3204_rset( 16, 0x1d );    // Unmute HPL , 29dB gain
AIC3204_rset( 17, 0x3a );    // Unmute HPR , -6dB gain
AIC3204_rset(  9, 0x30 );    // Power up HPL,HPR
AIC3204_rset( 10, 0x33 );    // HP powered from LDOIN, CM voltage = 1.65V
AIC3204_rset(  0, 0x00 );    // Select page 0
USBSTK5515_wait( 500 );       // Wait
AIC3204_rset( 16, 15 );       // Unmute HPL set gain
AIC3204_rset( 17, 00 );       // Unmute HPR set gain
/* ADC ROUTING and Power Up */
AIC3204_rset( 0, 1 );          // Select page 1
//AIC3204_rset( 51, 0x40 );    // Mic Bias ON
AIC3204_rset( 52, 0x10 );    //IN2L is routed to Left MICPGA with 40K resistance
AIC3204_rset( 55, 0x00 );    //IN2R is not routed to Right MICPGA
AIC3204_rset( 54, 0x03 );    // CM is routed to Left MICPGA via CM2L with 40K resistance
AIC3204_rset( 57, 0x00 );    // CM is not routed to Right MICPGA
AIC3204_rset( 59, 0x80 );       // MIC_PGA_L unmute
AIC3204_rset( 60, 0x80 );       // MIC_PGA_R unmute
AIC3204_rset( 0, 0 );       // Select page 0
AIC3204_rset( 81, 0xa0 );    // Powerup Left and Right ADC
AIC3204_rset( 82, 0x04 );    // Unmute Left and Right ADC
// I2S settings
I2S0_SRGR = 0x0;    //I2Sn Sample Rate Generator Register slave mode is invalide
I2S0_CR = 0x9011; // 16-bit word, slave, enable I2C Mono mode
//I2S2_CR = 0x9811;
//I2S0_CR = 0x8010;
// I2S0_CR Address:  0x2800 ((I2S BUS)  I2Sn Serializer Control Register (I2SSCTRL)
// +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
// |15:14:13:12|11:10: 9: 8| 7: 6: 5: 4| 3: 2: 1: 0|  <<== Bit Position
// +--+--+--+--+--+--+--+--+--+--+--+--+--+--:--:--+
// |rw:rw:rw:rw|rw:rw:rw:rw|rw:rw:rw:rw|rw:rw:rw:rw|  <<== Read / Write Access
// +--+--+--+--+--+--+--+--+--+--+--+--+--+--:--:--+
// | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0|  <<== Reset Values
// +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
// +--+--+--+--+--+--+--+--+--+--+--+--+--+--:--:--+
// | 1  0: 0: 1| 0: 0: 0: 0| 0: 0: 0: 1| 0: 0: 0: 1|  <<== current Values
// +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
// |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |
// |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  +-- [0]  FRMT             (0:I2S/left-justified format, 1:DSP format)
// |  |  |  |  |  |  |  |  |  |  |  |  |  |  +----- [1]  MODE             (0:Serializer is configured as a slave, 1:master)
// |  |  |  |  |  |  |  |  |  |  |  |  |  +-------- [2]  WDLNGTH          (0:clk active, 1:clk disabled)
// |  |  |  |  |  |  |  |  |  |  |  |  +----------- [3]  WDLNGTH          Choose serializer word length 8 10 .. 32
// |  |  |  |  |  |  |  |  |  |  |  |
// |  |  |  |  |  |  |  |  |  |  |  +-------------- [4]  WDLNGTH
// |  |  |  |  |  |  |  |  |  |  +----------------- [5]  WDLNGTH
// |  |  |  |  |  |  |  |  |  +-------------------- [6]  SIGN_EXT       (0:No sign extension, 1:Received data is sign extended. Transmit data is expected to be sign extended.For more information about sign extension)
// |  |  |  |  |  |  |  |  +----------------------- [7]  PACK             (0:Data packing mode disabled, 1:Data packing mode enabled)
// |  |  |  |  |  |  |  |
// |  |  |  |  |  |  |  +-------------------------- [8]  DATADLY          (0:1-bit data delay, 1:2-bit data delay)
// |  |  |  |  |  |  +----------------------------- [9]  CLKPOL          (0:Controls I2S clock polarity, 1:.....XXX $$$ )
// |  |  |  |  |  +-------------------------------- [10] FSPOL          (0:Inverts I2S frame-synchronization polarity, 1:....XXX $$$)
// |  |  |  |  +----------------------------------- [11] LOOPBACK       (0:Normal operation, no loopback, 1:Digital Loopback mode enabled)
// |  |  |  |
// |  |  |  +-------------------------------------- [12] MONO             (0:Stereo mode, 1:Mono mode. Valid only when bit 0, FRMT=1 (DSP Format))
// |  |  +----------------------------------------- [13] Reserved
// |  +-------------------------------------------- [14] Reserved
// +----------------------------------------------- [15] ENABLE          (0:I2S disabled, 1:I2S enabled)
I2S0_ICMR = 0x17; // Enable interrupts
//I2S0_ICMR = 0x3f;
// I2SINTMASK Address:  0x2814 ((I2S BUS)  I2Sn Interrupt Mask Register (I2SINTMASK)
// +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
// |15:14:13:12|11:10: 9: 8| 7: 6: 5: 4| 3: 2: 1: 0|  <<== Bit Position
// +--+--+--+--+--+--+--+--+--+--+--+--+--+--:--:--+
// |rw:rw:rw:rw|rw:rw:rw:rw|rw:rw:rw:rw|rw:rw:rw:rw|  <<== Read / Write Access
// +--+--+--+--+--+--+--+--+--+--+--+--+--+--:--:--+
// | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0|  <<== Reset Values
// +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
// +--+--+--+--+--+--+--+--+--+--+--+--+--+--:--:--+
// | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 1| 0: 1: 0: 0|  <<== current Values
// +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
// |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |
// |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  +-- [0]  OUERR          (0:Disable overrun/underrun error interrupt, 1:Enable overrun/underrun error interrupt.)
// |  |  |  |  |  |  |  |  |  |  |  |  |  |  +----- [1]  FERR             (0:Disable frame-synchronization error interrupt, 1:Enable frame-synchronization error interrupt.)
// |  |  |  |  |  |  |  |  |  |  |  |  |  +-------- [2]  RCVMON          (0:Disable mono RX data interrupt, 1:Enable mono RX data interrupt.)
// |  |  |  |  |  |  |  |  |  |  |  |  +----------- [3]  RCVST          (0:Disable stereo RX data interrupt, 1:Enable stereo RX data interrupt)
// |  |  |  |  |  |  |  |
// |  |  |  |  |  |  |  |  |  |  |  |
// |  |  |  |  |  |  |  |  |  |  |  +-------------- [4]  XMITMON          (0:Disable mono TX data interrupt, 1:Enable mono TX data interrupt)
// |  |  |  |  |  |  |  |  |  |  +----------------- [5]  XMITST          (0:Disable stereo TX data interrupt, 1:Enable stereo TX data interrupt)
// |  |  |  |  |  |  |  |  |  +-------------------- [6]  Reserved
// |  |  |  |  |  |  |  |  +----------------------- [7]  Reserved
// |  |  |  |  |  |  |  |
// |  |  |  |  |  |  |  +-------------------------- [8]  Reserved
// |  |  |  |  |  |  +----------------------------- [9]  Reserved
// |  |  |  |  |  +-------------------------------- [10] Reserved
// |  |  |  |  +----------------------------------- [11] Reserved
// |  |  |  |
// |  |  |  +-------------------------------------- [12] Reserved
// |  |  +----------------------------------------- [13] Reserved
// |  +-------------------------------------------- [14] Reserved
// +----------------------------------------------- [15] Reserved
]

qwe041

2019-8-14 10:42:20

默认状态下这些是关闭的。 IN1/L 和IN1/R bypass到输出HPL HPR的这路寄存器是 P1_R12_B2 和P1_R13_B2
通过MICPGA 过来的是 Mixer Amplifier Control 路径，电源开关在P1_R9_B1/0, 混音位置在P1_R12_B1/0 和P1_R13_B1。
MICPGA 对应的是标有 0。。。。。。+47.5dB的 PGA
MAL/MAR 对应的是标有+30。。。0dB的PGA --- 用来做Bypass

潘璐

2019-8-14 10:58:59

引用: qwe041 发表于 2019-8-14 16:13
默认状态下这些是关闭的。 IN1/L 和IN1/R bypass到输出HPL HPR的这路寄存器是 P1_R12_B2 和P1_R13_B2
通过MICPGA 过来的是 Mixer Amplifier Control 路径，电源开关在P1_R9_B1/0, 混音位置在P1_R12_B1/0 和P1_R13_B1。
MICPGA 对应的是标有 0。。。。。。+47.5dB的 PGA

HPL有一个很奇怪的问题，就是前文中我提到的耳机中听到的pc播放的声音，我把IN1L，MAL，LDAC，MAR都关闭，在HPL中还是可以听到PC播放的声音，
请问这个声音是从哪里来的呢？图中的CM HP是什么，这个声音是不是从这里来的？具体配置如下：
AIC3204_rset( 0, 0x01 );      // Select page 1
    AIC3204_rset( 12, 0x00 );      // LDAC AFIR routed to HPL
AIC3204_rset( 13, 0x08 );      // RDAC AFIR routed to HPR

qwe041

2019-8-14 11:05:40

引用: hyqopen 发表于 2019-8-14 16:29
HPL有一个很奇怪的问题，就是前文中我提到的耳机中听到的pc播放的声音，我把IN1L，MAL，LDAC，MAR都关闭，在HPL中还是可以听到PC播放的声音，
请问这个声音是从哪里来的呢？图中的CM HP是什么，这个声音是不是从这里来的？具体配置如下：
AIC3204_rset( 0, 0x01 ); // Select page 1

如果你听见的声音是很小的，是因为左右声道的串扰导致。确认另一个声道的声音没有开到很大。一般5mW是正常。你可以将DACLmute住这样也能证明声音不是从DAC进入。

潘璐

2019-8-14 11:23:06

引用: qwe041 发表于 2019-8-14 16:36
如果你听见的声音是很小的，是因为左右声道的串扰导致。确认另一个声道的声音没有开到很大。一般5mW是正常。你可以将DACLmute住这样也能证明声音不是从DAC进入。

现在这个旁路声音已经没有了，
我对比了一下之前的配置和现在的配置，DACL和DACR都是使用默认值，我主要是对时钟部分做了调整，把MADC和MADC，DOSR和AOSR调为不一样，
void aic3204_init_different_mono(void)
[
   SYS_EXBUSSEL = 0x6100;         // Enable I2C bus
   USBSTK5515_I2C_init( );        // Initialize I2C
    /* Configure AIC3204 */
    AIC3204_rset( 0, 0x00 );          // Select page 0
    AIC3204_rset( 1, 0x01 );          // Reset codec
    AIC3204_rset( 0, 0x01 );          // Select page 1
    AIC3204_rset( 1, 0x08 );          // Disable crude AVDD generation from DVDD
    AIC3204_rset( 2, 0x01 );          // Enable Analog Blocks, use LDO power
    AIC3204_rset( 10, 0x00 );        //#Set the input common mode to 0.9V
    AIC3204_rset( 61, 0x00 );        //#Set ADC PTM_R4
    AIC3204_rset( 71, 0x00 );        //#Set MicPGA startup delay to 3.1ms
    AIC3204_rset( 123, 0x01 );       //#Set the REF charging time to 40ms

    /* PLL and Clocks config and Power Up */
    AIC3204_rset( 0, 0 );          // Select page 0
    AIC3204_rset( 27, 0x4d );       // BCLK and WCLK is set as o/p to AIC3204(Master) interface DSP
    AIC3204_rset( 28, 0x02 );       //#Data offset value ( ajout de 1 BCLK's)
    AIC3204_rset( 29, 0x08 );       //# Audio interface set
    AIC3204_rset( 61, 0x01 );       //ADC Signal Processing Block Control Register
    AIC3204_rset( 60, 0x8 );        //DAC Signal Processing Block Control Register
    AIC3204_rset( 4, 3 );          // PLL setting: PLLCLK <- MCLK, CODEC_CLKIN <-PLL CLK
    AIC3204_rset( 6, 8 );          // PLL setting: J=8
    AIC3204_rset( 7, 0x07 );       // PLL setting: HI_BYTE(D=1680)
    AIC3204_rset( 8, 0x80 );       // PLL setting: LO_BYTE(D=1680)
    AIC3204_rset( 30, 0xc0 );      // For 32 bit clocks per frame in Master mode ONLY
                                   // BCLK=DAC_CLK/N =(12288000/8) = 1.536MHz = 32*fs
    AIC3204_rset( 5, 0x91 );       // PLL setting: Power up PLL, P=1 and R=1
    AIC3204_rset( 13, 03 );        // Hi_Byte(DOSR) for DOSR = 768 decimal or 0x0300 DAC oversamppling
    AIC3204_rset( 14, 0x00 );      // Lo_Byte(DOSR) for DOSR = 768 decimal or 0x0300
    AIC3204_rset( 20, 0x80 );      // AOSR for AOSR = 128 decimal or 0x80 for decimation filters 1 to 6
    AIC3204_rset( 11, 0x88 );      // Power up NDAC and set NDAC value to 2
    AIC3204_rset( 12, 0x82 );      // Power up MDAC and set MDAC value to 8
    AIC3204_rset( 18, 0x88 );      // Power up NADC and set NADC value to 8
    AIC3204_rset( 19, 0x8c );      // Power up MADC and set MADC value to 12

    AIC3204_rset( 81, 0x00 ); // Power down Left and Right ADC
    AIC3204_rset( 63, 0x14 ); // Power down left,right data paths and set channel
    AIC3204_rset( 61, 2 );       // PRB_R2
    // set biquad A to low pass fc = 3628
    AIC3204_rset( 0, 8 ); // Select page 8
    AIC3204_rset( 36, 0x6A ); // Left N0 H
    AIC3204_rset( 37, 0xC3 ); // Left N0 M
    AIC3204_rset( 38, 0x6F ); // Left N0 L
    AIC3204_rset( 40, 0x35 ); // Left N1 H
    AIC3204_rset( 41, 0x61 ); // Left N1 M
    AIC3204_rset( 42, 0xB7 ); // Left N1 L
    AIC3204_rset( 44, 0x00 ); // Left N2 H
    AIC3204_rset( 45, 0x00 ); // Left N2 M
    AIC3204_rset( 46, 0x00 ); // Left N2 L
    AIC3204_rset( 48, 0xD5 ); // Left D1 H
    AIC3204_rset( 49, 0x3C ); // Left D1 M
    AIC3204_rset( 50, 0x91 ); // Left D1 L
    AIC3204_rset( 52, 0x00 ); // Left D2 H
    AIC3204_rset( 53, 0x00 ); // Left D2 M
    AIC3204_rset( 54, 0x00 ); // Left D2 L

    AIC3204_rset( 0, 9 ); // Select page 9
    AIC3204_rset( 44, 0x6F ); // Right N0 H
    AIC3204_rset( 45, 0x96 ); // Right N0 M
    AIC3204_rset( 46, 0x52 ); // Right N0 L
    AIC3204_rset( 48, 0x37 ); // Right N1 H
    AIC3204_rset( 49, 0xCB ); // Right N1 M
    AIC3204_rset( 50, 0x29 ); // Right N1 L
    AIC3204_rset( 52, 0x00 ); // Right N2 H
    AIC3204_rset( 53, 0x00 ); // Right N2 M
    AIC3204_rset( 54, 0x00 ); // Right N2 L
    AIC3204_rset( 56, 0xD0 ); // Right D1 H
    AIC3204_rset( 57, 0x69 ); // Right D1 M
    AIC3204_rset( 58, 0xAD ); // Right D1 L
    AIC3204_rset( 60, 0x00 ); // Right D2 H
    AIC3204_rset( 61, 0x00 ); // Right D2 M
    AIC3204_rset( 62, 0x00 ); // Right D2 L

    /* DAC ROUTING and Power Up */
    AIC3204_rset( 0, 0x01 );      // Select page 1
    AIC3204_rset( 9, 0x30 );       //# OUTPUT DRIVER POWER CONTROL hp->ON lineout->OFF mixer->OFF
    AIC3204_rset( 10, 0x03 );      //#COMMON MODE CONTROL REGISTER Output of HP is powered by LDOIN
    AIC3204_rset( 11, 0x10 );      //Over Current detection is enabled for HPL & HPR
    AIC3204_rset( 12, 0x08 );      //# Left DAC (+) -> HPL
    AIC3204_rset( 13, 0x00 );      //# Left DAC (-) -> HPR
    AIC3204_rset( 14, 0x00 );      //# LOL is not routed
    AIC3204_rset( 15, 0x00 );      //# LOR is not routed
    AIC3204_rset( 16, 0x3c );      // HPL Driver gain setting register Unmute HPL , 0dB gain
    AIC3204_rset( 17, 0x3c );      // volume de sortie headphone 0x00 -> 0dB 0x3A -> -6dB 0x1d -> +29dB
    AIC3204_rset( 18, 0x40 );     //# LOL driver gain settings register
    AIC3204_rset( 19, 0x40 );     //# LOL & LOR MUTED
    AIC3204_rset( 20, 0x25 );     //#HEADPHONE DRIVER STARTUP Headphone amps power up slowly in 5.0 time constants / Headphone amps power up time is determined with 6K resistance
    AIC3204_rset( 22, 0x00 );     //# IN1L to HPL volume control bypass 0dB
    AIC3204_rset( 23, 0x00 );     //# IN1L to HPL volume control bypass 0dB
    AIC3204_rset( 24, 0x00 );     //# MIXERAMP Left volume control
    AIC3204_rset( 25, 0x00 );
    AIC3204_rset( 51, 0x50 );      //# setting du micbias micbias = Vcc
    AIC3204_rset( 0, 0x00 );      // Select page 0
    AIC3204_rset( 64, 0x00 );      //#DAC L UNMUTED, R&L independant DAC R MUTED (mode differentiel)
                                   //# 0x00 -> 0dB 0xFF -> -0.5dB 0x81 -> -63dB
    AIC3204_rset( 65, 0x00 );      //# Left DAC channel digital volume control register
    AIC3204_rset( 66, 0x00 );      //# Right DAC Channel Digital Volume Control Register
    AIC3204_rset( 63, 0x90 );      //#DAC L switched ON, R OFF, soft-stepping enabled

    /* ADC ROUTING and Power Up */
    AIC3204_rset( 0, 1 );          // Select page 1
    AIC3204_rset( 52, 0x30 );      //# IN2L -> Left MICPGA +   40K resistance
    AIC3204_rset( 54, 0x30 );      //# IN2R -> Left MICPGA - 40K resistance
    AIC3204_rset( 55, 0x00 );      //# Right MICPGA positive terminal input routing
    AIC3204_rset( 57, 0x00 );      //# Right MICPGA negative terminal input routing
    AIC3204_rset( 58, 0xbb );      //#Floating Input Configuration register
    AIC3204_rset( 59, 0 );         // MIC_PGA_L unmute
    AIC3204_rset( 60, 0 );         // MIC_PGA_R unmute
    AIC3204_rset( 0, 0 );          // Select page 0
    AIC3204_rset( 81, 0x80 );     //#ADC right OFF & left ON
    AIC3204_rset( 82, 0x08 );     //#ADC left UNMUTED right MUTED
    AIC3204_rset( 83, 0x67 );     //#ADC left & right channel volume control
    AIC3204_rset( 84, 0x67 );     //#ADC volume 20dB -- 0x28    -12dB -- 0x67
    AIC3204_rset( 85, 0x81 );     //#ADC phase adjust register

    AIC3204_rset( 0, 0 );
    USBSTK5515_wait( 200 );        // Wait

    // I2S settings
    I2S0_SRGR = 0x0;      //I2Sn Sample Rate Generator Register slave mode is invalide
    //I2S0_CR = 0x9011;    // 16-bit word, slave, enable I2C Mono mode
    //I2S2_CR = 0x9e11;
    I2S0_CR = 0x8010;
    // I2S0_CR   Address: 0x2800 ((I2S BUS) I2Sn Serializer Control Register (I2SSCTRL)
    // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
    // |15:14:13:12|11:10: 9: 8| 7: 6: 5: 4| 3: 2: 1: 0| <<== Bit Position
    // +--+--+--+--+--+--+--+--+--+--+--+--+--+--:--:--+
    // |rw:rw:rw:rw|rw:rw:rw:rw|rw:rw:rw:rw|rw:rw:rw:rw| <<== Read / Write Access
    // +--+--+--+--+--+--+--+--+--+--+--+--+--+--:--:--+
    // | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| <<== Reset Values
    // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
    // +--+--+--+--+--+--+--+--+--+--+--+--+--+--:--:--+
    // | 1 0: 0: 1| 0: 1: 1: 0| 0: 0: 0: 1| 0: 0: 0: 1| <<== current Values
    // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
    //   | | | | | | | | | | | | | | | |
    //   | | | | | | | | | | | | | | | +-- [0] FRMT              (0:I2S/left-justified format, 1:DSP format)
    //   | | | | | | | | | | | | | | +----- [1] MODE              (0:Serializer is configured as a slave, 1:master)
    //   | | | | | | | | | | | | | +-------- [2] WDLNGTH           (0:clk active, 1:clk disabled)
    //   | | | | | | | | | | | | +----------- [3] WDLNGTH           Choose serializer word length 8 10 .. 32
    //   | | | | | | | | | | | |
    //   | | | | | | | | | | | +-------------- [4] WDLNGTH
    //   | | | | | | | | | | +----------------- [5] WDLNGTH
    //   | | | | | | | | | +-------------------- [6] SIGN_EXT          (0:No sign extension, 1:Received data is sign extended. Transmit data is expected to be sign extended.For more information about sign extension)
    //   | | | | | | | | +----------------------- [7] PACK              (0:Data packing mode disabled, 1:Data packing mode enabled)
    //   | | | | | | | |
    //   | | | | | | | +-------------------------- [8] DATADLY           (0:1-bit data delay, 1:2-bit data delay)
    //   | | | | | | +----------------------------- [9] CLKPOL            (0:Controls I2S clock polarity, 1:.....XXX $$$ )
    //   | | | | | +-------------------------------- [10] FSPOL             (0:Inverts I2S frame-synchronization polarity, 1:....XXX $$$)
    //   | | | | +----------------------------------- [11] LOOPBACK          (0:Normal operation, no loopback, 1:Digital Loopback mode enabled)
    //   | | | |
    //   | | | +-------------------------------------- [12] MONO              (0:Stereo mode, 1:Mono mode. Valid only when bit 0, FRMT=1 (DSP Format))
    //   | | +----------------------------------------- [13] Reserved
    //   | +-------------------------------------------- [14] Reserved
    //   +----------------------------------------------- [15] ENABLE            (0:I2S disabled, 1:I2S enabled)
    //I2S0_ICMR = 0x17;    // Enable interrupts
    I2S0_ICMR = 0x2b;
    // I2SINTMASK   Address: 0x2814 ((I2S BUS) I2Sn Interrupt Mask Register (I2SINTMASK)
    // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
    // |15:14:13:12|11:10: 9: 8| 7: 6: 5: 4| 3: 2: 1: 0| <<== Bit Position
    // +--+--+--+--+--+--+--+--+--+--+--+--+--+--:--:--+
    // |rw:rw:rw:rw|rw:rw:rw:rw|rw:rw:rw:rw|rw:rw:rw:rw| <<== Read / Write Access
    // +--+--+--+--+--+--+--+--+--+--+--+--+--+--:--:--+
    // | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| <<== Reset Values
    // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
    // +--+--+--+--+--+--+--+--+--+--+--+--+--+--:--:--+
    // | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 1| 0: 1: 0: 0| <<== current Values
    // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
    //   | | | | | | | | | | | | | | | |
    //   | | | | | | | | | | | | | | | +-- [0] OUERR             (0:Disable overrun/underrun error interrupt, 1:Enable overrun/underrun error interrupt.)
    //   | | | | | | | | | | | | | | +----- [1] FERR              (0:Disable frame-synchronization error interrupt, 1:Enable frame-synchronization error interrupt.)
    //   | | | | | | | | | | | | | +-------- [2] RCVMON            (0:Disable mono RX data interrupt,   1:Enable mono RX data interrupt.)
    //   | | | | | | | | | | | | +----------- [3] RCVST             (0:Disable stereo RX data interrupt, 1:Enable stereo RX data interrupt)
    //   | | | | | | | |
    //   | | | | | | | | | | | |
    //   | | | | | | | | | | | +-------------- [4] XMITMON           (0:Disable mono TX data interrupt, 1:Enable mono TX data interrupt)
    //   | | | | | | | | | | +----------------- [5] XMITST            (0:Disable stereo TX data interrupt, 1:Enable stereo TX data interrupt)
    //   | | | | | | | | | +-------------------- [6] Reserved
    //   | | | | | | | | +----------------------- [7] Reserved
    //   | | | | | | | |
    //   | | | | | | | +-------------------------- [8] Reserved
    //   | | | | | | +----------------------------- [9] Reserved
    //   | | | | | +-------------------------------- [10] Reserved
    //   | | | | +----------------------------------- [11] Reserved
    //   | | | |
    //   | | | +-------------------------------------- [12] Reserved
    //   | | +----------------------------------------- [13] Reserved
    //   | +-------------------------------------------- [14] Reserved
    //   +----------------------------------------------- [15] Reserved
]

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