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王晋

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[问答]

如何同步54LP的ADC?

亲爱的先生:
可以通过外部CLK同步多个54 LP芯片吗?如果可以,它的同步精度如何?微米秒?非常感谢。
当做
年轻的

以上来自于百度翻译


     以下为原文
  Dear sir:
         Could many 54LP chips be synchronized by an external clk? If can be, how about its synchronization accuracy? micron sec ? Thank you very much.
        Regards
        young

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王琳

2019-7-30 13:00:15
同步PSoC的时钟已经讨论过,这是不可能的。
但从几个PSoCs ADCs可以通过发送一个外部SOC信号传送到ADC完成。
因为(总是一个很好的做法)这个信号是同步的内部时钟,你可能会去一到两个时钟周期,在60MHz像30ns运行时。从那里startsmay ADC实际上取决于预分频点(我不是与ADC内部相当)但不会超过因子4。所以你可以很确定在同一微秒启动ADC。
如果这是不足够的,创建一个所谓的“例如我”:在这页的顶部- >;支持&;社区>;技术支持- >;创建一个例如我。
鲍勃

以上来自于百度翻译


     以下为原文
  Synchronizing the PSoC's clocks was discussed before, that was not possible.
    But STARTING the ADCs of several PSoCs can be done by sending out an external SOC-signal that is routed to the ADCs.
    Since (as always a good practice) this signal is synchronized to the internal clock you may be off for one to two clock cycles which is when running at 60MHz something like 30ns. The point from where the ADC actually starts may depend on a pre-divider (I am not quite fit with the ADC internals) but that will not be more than factor 4. So you can be quite sure to start your ADCs within the same microsecond.
    If this is not sufficent, create a so-called "MyCase": At top of this page -> Support&Community->Technical Support ->Create a MyCase.
     
    Bob
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凌流浪

2019-7-30 13:39:39
你好,专家:
许多psoc5 ADCs(如果我最后选择芯片为控制器)需要同步和采样频率将约1-4千赫。外部选通信号将触发ADC转换。我需要知道CY8C54能完成这项任务。
非常感谢。
当做。
年轻的

以上来自于百度翻译


     以下为原文
  HI,expert::
        The ADCs of many PSOC5 (if I finally choose the chip as the controller) need to be synchronized, and the sample frequency will be about 1-4 KHz. The external strobe signal will trigger the conversion of ADC. I need to know if the CY8C54LP could fulfill the task.
        Thank you very much.
        Regards.
        Young
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杨军

2019-7-30 13:55:21
你可以申请一个案子来检查我,但我相信SAR有
固定采样时间前端与Delsig。所以如果你想尝试
与此同时SAR会组成多个信号
选择的。或者使用单独的S/H并同步它们,以便使用。
DelSig。这是在创建者中的SAMPE跟踪和保持组件。
注意你当然要考虑噪音和下垂/准确性权衡
S/H方法。
问候,Dana。

以上来自于百度翻译


     以下为原文
  You might file a CASE to check me on this, but I believe the SAR has
    a fixed sampling time front end vs the DelSig. So if you are trying to sample
    several signals at precisely the same time SAR would be component
    of choice. Or use separate S/H and synch them so that you can use
    DelSig. Thats the Sampe Track and Hold component in Creator.
     
    Note of course you have to consider noise and droop/accuracy tradeoffs
    of the S/H approach.
     
    Regards, Dana.
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王琳

2019-7-30 14:12:19
CY8C54-LP系列不包含Delsig ADC
鲍勃

以上来自于百度翻译


     以下为原文
  The CY8C54-LP family doesn't contain a DelSig ADC
     
    Bob
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