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[问答]

在VHDL中使用Xilinx出现错误

我在VHDL中使用Xilinx,我使用Coregen生成FIFO。
现在我正在尝试使用它...我想将500个数据存储到FIFO中并读取它...
我的FIFO工作但只能存储1个数据,所以它没用...
我有一个类似的代码,使用BUTTON2来读取FIFO ......
模拟工作但不是实现...我加入代码......
问:您对此错误的来源有任何提示或想法吗?
提前致谢 !
FIFO_OUTPUT.zip 1397 KB

以上来自于谷歌翻译


以下为原文

I'm working with Xilinx in VHDL and I used Coregen to generate a FIFO. Now I'm trying to use it... I would like to store like 500 datas into a FIFO and read it...
My FIFO works but can only store 1 data so it's useless...

And I've a similar code using a BUTTON2 that is used to read the FIFO...

The simulation is working but not the implementation... I join the codes...

Q : Do you have any tips or ideas of where this error could come from?

Thanks in advance !
            FIFO_OUTPUT.zip ‏1397 KB

回帖(3)

杨涛

2019-7-29 12:24:03
嗨@ fmousse,你的意思是“模拟工作但不是实施”?
你是说你没有在电路板上获得相同的输出?
因为实现成功通过。谢谢,Nupur
谢谢,Nupur -----------------------------------------------
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Hi @fmousse,

What do you mean by "The simulation is working but not the implementation"?  Do you mean you are not obtaining the same output on the board? Because the implementation is passing successfully.

Thanks,
NupurThanks,
Nupur
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孔喆

2019-7-29 12:41:10
嗨@ nupurs,是的,我使用电路板没有相同的结果...... VHDL语法似乎没问题?
我自己学习了VHDL,所以我没有很多建议......

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Hi @nupurs, yes it's that, I don't have the same result using the board... The VHDL syntax seems ok? I learned VHDL by myself so I havn't had a lot of advices...
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孔喆

2019-7-29 12:59:26
我认为第一个问题是我没有去抖动,我试着这样做,但我现在还不能,我会再试一次......

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I think that a first problem is that I have no debouncer, I try to do it but I'm not able at the moment, I'll try again...
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