嗨Bhal，
没门。
你会发现很多关于“门数”主题的线索。
但这里还有一件重要的事情。
如果某些HDL通过ASIC工具创建一些标准单元实现，则没有独特的结果。
这取决于综合约束。
您可以从ISE综合中了解到，您可以在区域和速度之间进行选择。
ASIC工具也是如此，它们有更多的选择，因为电路可以分解为单个门而不是LUT。
desingn库的选择也有影响。
所以忘了它。
让工厂的设计师完成他们的工作，他们会告诉你最终的结果。
最好花时间为晶圆厂人员提供良好的设计要求。
（时钟频率，功率限制，驱动强度，I / O时序（！）等）
亲切的问候
Eilert
以上来自于谷歌翻译
以下为原文
Hi Bhal,
no way.
You will find a lot of threads about the "gate count" topic.
But here's even one more thing important.
If some HDL goes through the ASIC tools to create some standard cell implementation there's no unique result.
It depends on the synthesis constraints.
You know from the ISE synthesis that you can choos between area and speed.
Same goes for ASIC tools and they have much more options, since the circuits are brocen down to single gates instead of LUTs. And the choice of the desingn library also has an influence.
So just forget it.
Let the designers at the fab do their work and they will tell you the final result.
Better spend your time providing the fab people with good design requirements.
(clock frequency, power limits, drive strength, I/O timings(!) etc.)
Kind regards
Eilert
嗨Bhal，
没门。
你会发现很多关于“门数”主题的线索。
但这里还有一件重要的事情。
如果某些HDL通过ASIC工具创建一些标准单元实现，则没有独特的结果。
这取决于综合约束。
您可以从ISE综合中了解到，您可以在区域和速度之间进行选择。
ASIC工具也是如此，它们有更多的选择，因为电路可以分解为单个门而不是LUT。
desingn库的选择也有影响。
所以忘了它。
让工厂的设计师完成他们的工作，他们会告诉你最终的结果。
最好花时间为晶圆厂人员提供良好的设计要求。
（时钟频率，功率限制，驱动强度，I / O时序（！）等）
亲切的问候
Eilert
以上来自于谷歌翻译
以下为原文
Hi Bhal,
no way.
You will find a lot of threads about the "gate count" topic.
But here's even one more thing important.
If some HDL goes through the ASIC tools to create some standard cell implementation there's no unique result.
It depends on the synthesis constraints.
You know from the ISE synthesis that you can choos between area and speed.
Same goes for ASIC tools and they have much more options, since the circuits are brocen down to single gates instead of LUTs. And the choice of the desingn library also has an influence.
So just forget it.
Let the designers at the fab do their work and they will tell you the final result.
Better spend your time providing the fab people with good design requirements.
(clock frequency, power limits, drive strength, I/O timings(!) etc.)
Kind regards
Eilert
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