没有ucf，
这些工具不知道放置IO引脚的位置，因此它们会将它们放在最容易使设计有效（工作）的地方。
在没有任何时序限制的情况下，通过将设计扩展到利用所有互连，而不考虑性能，这些工具将完成最少量的工作。
结果将以它报告的时钟频率工作，但这可能非常慢，因为你没有要求它做任何事情。
它的完成速度非常快，因为你没有努力满足约束。
作为一般规则，您始终没有约束。
一旦看到放置IO的最佳位置，就将这些位置放在ucf中。
然后，您约束时钟周期以满足性能目标。
如果您需要更改Io位置，请更改IO位置。
然后，只有这样，你才会发布原理图来制作印刷电路板。
然后，您可以返回并添加到您的设计中，进行更改，并确信IO引脚不需要更改，并且设计将满足所有时序要求。
Austin Lesea主要工程师Xilinx San Jose
以上来自于谷歌翻译
以下为原文
Without the ucf,
The tools don't know where to put IO pins, so they will put them where it is easiest to make the design valid (work).
Without any timing constraints, the tools will do the least amount of work, by spreading the design out to take advantage of all the interconnect, with no regard to performance. The result will work at the clock frequency it reports, but that may very very slow, as you did not ask it to do anything.
It will be very fast in finishing, as you didn't make it work hard to meet constraints.
As a general rule, you always start with no constraints. Once you see the best place to put IO's, you put those locations in the ucf. Then you constrain the clock periods to meet performance goals. If you need to change Io placement, you change IO placement. Then, and only then, do you release a schematic to make a printed ciruit board. You may then go back and add to your design, make changes, with some confidence that IO pins will not need to change, and the design will meet all timing requirements.
Austin Lesea
Principal Engineer
Xilinx San Jose
没有ucf，
这些工具不知道放置IO引脚的位置，因此它们会将它们放在最容易使设计有效（工作）的地方。
在没有任何时序限制的情况下，通过将设计扩展到利用所有互连，而不考虑性能，这些工具将完成最少量的工作。
结果将以它报告的时钟频率工作，但这可能非常慢，因为你没有要求它做任何事情。
它的完成速度非常快，因为你没有努力满足约束。
作为一般规则，您始终没有约束。
一旦看到放置IO的最佳位置，就将这些位置放在ucf中。
然后，您约束时钟周期以满足性能目标。
如果您需要更改Io位置，请更改IO位置。
然后，只有这样，你才会发布原理图来制作印刷电路板。
然后，您可以返回并添加到您的设计中，进行更改，并确信IO引脚不需要更改，并且设计将满足所有时序要求。
Austin Lesea主要工程师Xilinx San Jose
以上来自于谷歌翻译
以下为原文
Without the ucf,
The tools don't know where to put IO pins, so they will put them where it is easiest to make the design valid (work).
Without any timing constraints, the tools will do the least amount of work, by spreading the design out to take advantage of all the interconnect, with no regard to performance. The result will work at the clock frequency it reports, but that may very very slow, as you did not ask it to do anything.
It will be very fast in finishing, as you didn't make it work hard to meet constraints.
As a general rule, you always start with no constraints. Once you see the best place to put IO's, you put those locations in the ucf. Then you constrain the clock periods to meet performance goals. If you need to change Io placement, you change IO placement. Then, and only then, do you release a schematic to make a printed ciruit board. You may then go back and add to your design, make changes, with some confidence that IO pins will not need to change, and the design will meet all timing requirements.
Austin Lesea
Principal Engineer
Xilinx San Jose
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