如何才能将8位数据从FPGA发送到PC？

嗨，
你的描述并不完全清楚你的问题。
但这里有一些提示：
你是如何填补BRAM的？
你用过一些UART吗？
要与PC通信，您还可以使用UART。
BRAM可以在双端口模式下使用，因此您可以同时从控制器和PC访问它。
如果那是不可能的，例如
因为您的系统已经使用了第二个端口，您需要一些在控制器和PC访问之间切换的访问控制，这不是问题，因为RAM访问时间远远高于UART传输速度。
有一个很好的综合 
Eilert



以下为原文

Hi,
your problem is not entirely clear from your description.
But here are some hints:
How have you filled the BRAM? Have you used some UART?
For communication with the PC you can also use a UART.
 
A BRAM can be used in Dual-Port mode, so you can access it from the controller and the PC at the same time.
If that is not possible, e.g. because the second port is already used by your system,  you need some access controll that switches between controller and PC access, which isn't a problem, because RAM access time is much higher than UART transmission speed.
 
Have a nice synthesis
  Eilert

嗨专家， 
我从外部控制器填充了256x8 BRAM。
并且必须将相同的数据发送到PC。
现在我使用BRAM的超频为16.6Mhz（60.24 ns）。
每60.24纳秒，一个数据将从RAM发出。
所以对于256个数据，256 x 60.24 nsec = 15.42 usec。
我可以将BRAM的data_out连接到UART输入吗？
我必须使用终端软件（如超级终端）在PC中查看数据。
超级终端将支持高达921600 bps。
要实现这一目标，
1.什么必须是UART的时钟？
2.什么是BRAM的退出时间可以选择？
请告诉我。
谢谢，
V. Prakash



以下为原文

Hi Expert,
 
        I had filled the 256x8 BRAM from External Controller. and the same data have to be sent to the PC.
 
now I am using out_clock of BRAM as 16.6Mhz (60.24 ns). For every 60.24 nsec, the one data will be sent out from the RAM. so for 256 data, 256 x 60.24 nsec = 15.42 usec .  Can i connect this data_out of BRAM to the UART input.? I have to see the data in the PC using terminal software like hyperterminal.
 
Hyperterminal will support upto 921600 bps. For this to be acheived,
1. what must be the clock to the UART?
2. what is the out_clock for the BRAM can be selected?
 
Please do let me know.
 
Thanks,
V. Prakash
 
 

嗨，
那么，你是如何从外部控制器中填充BRAM的？
你有没有把BRAM的地址和数据线等放到FPGA引脚上？
我的猜测是你的控制器也通过一些串行接口连接到FPGA。
在普通的RS232接口上实现921600波特的传输速度是困难的，但是现在PC-COM接口通常通过USB完成，需要在FPGA板上使用一些FTDI芯片（例如在某些Digilent Boards上：NEXYS3或ATLYS）。
实际上，RS232接口很少超出115K波特限制。
主要是因为软件和操作系统无法处理更高的速度。
FPGA内部的大多数UART-IP需要16倍的时钟波特率。
Tx部件（如果可拆分）通常能够仅使用波特率进行计时。
查看随Picoblaze（KCPSM3）提供的UART，了解HDL中的工作方式。
此外，即使接口能够传输数据，您如何能够读取到达终端窗口的内容？
有一个很好的综合 
Eilert



以下为原文

Hi,
just, how have you filled the BRAM from the external controller?
Have you put Adress and Data lines etc. of the BRAM to the FPGA pins?
My guess was that your controller is connected to the FPGA via some serial interface too.
 
Acheiving a transfer speed of 921600 Baud would be difficult on a normal RS232 Interface, however nowadays PC-COM interfaces are often done via USB, requiring some FTDI chip on your FPGA Board (e.g. like on some Digilent Boards: NEXYS3 or ATLYS).  Practically RS232 interfaces rarely go beyond the 115K Baud limit. Mostly because the software and OS can't deal with higher speeds.
 
Most UART-IPs inside the FPGA need 16 times the baudŕate for clocking.
The Tx parts (if splitable) often are capable of being clocked with just the baud rate.
Take a look at the UART that is provided with the Picoblaze (KCPSM3) to see how things are done in HDL.
 
Besides, even if the interfaces are capable of transfereing the data, how are you capable to read what arrives on the terminal window?
 
Have a nice synthesis
  Eilert
 
 

嗨专家，
那么，你是如何从外部控制器中填充BRAM的？
我从外部控制器填充了BRAM（256x8）。
外部控制器的8位端口连接到FPGA BRAM data_in（8位）。
12 usec时钟从FPGA到外部控制器生成。
在下降沿期间，数据将从外部控制器放置到FPGA。
在上升沿期间，数据将被带入FPGA BRAM。
“
你有没有把BRAM的地址和数据线等放到FPGA引脚上？
我使用了双端口RAM，带有独立的8位读地址计数器和8位写地址计数器。
BRAM的时钟和写地址计数器是相同的12 usec。
通过这种方式我填补了BRAM。
现在我必须将填充的数据发送到PC。
我的猜测是你的控制器也通过一些串行接口连接到FPGA。
不，我没有使用串行接口。
外部控制器的8位端口连接到FPGA BRAM输入，12个usec时钟同步。
此外，即使接口能够传输数据，您如何能够读取到达终端窗口的内容？
Windows中的超级终端将允许查看串行数据，波特率为921600 bps。
唯一的问题是，我必须实现串行接口才能看到BRAM中填充的数据。
UART是否有任何现成的vhdl代码。
请分享。
谢谢，
V. Prakash



以下为原文

Hi Expert,
 
just, how have you filled the BRAM from the external controller?


I had filled the BRAM(256x8) from the External controller. 8 bit port from the external controller is connected to the FPGA BRAM data_in(8 bit). 12 usec Clock is generated from the FPGA to External controller. During falling edge, data will be Placed  from  External controller  to FPGA. During raising edge data will be taken into the FPGA BRAM. '
 
Have you put Adress and Data lines etc. of the BRAM to the FPGA pins?
I had used dual port RAM with seperate 8 bit read address counter and 8 bit write address counter. clock to BRAM and write address counter are the same 12 usec. in this way i filled the BRAM. Now i have to sent the filled data to the PC.
 
My guess was that your controller is connected to the FPGA via some serial interface too.
No i didnt use serial interface. 8 bit port from external controller is connected to FPGA BRAM input with 12 usec clock to synchronize.

 
Besides, even if the interfaces are capable of transfereing the data, how are you capable to read what arrives on the terminal window?
Hyperterminal in windows will allow to see the serial data upto the baud rate of 921600 bps. only thing is, i have to implement the serial interface  to see the data filled in the BRAM. Is there any readymade vhdl code for UART. Please share.

 
Thanks,
V. Prakash