请问任何人都有过IO标准最适合LPDDR内存的经验吗？

不知何故，在查看信号完整性时，使用LVCMOS18 IO的Micron LPDDR存储器接口似乎不太好。
什么“不太好”意味着什么？
这是基于示波器波形还是电路仿真？
如果是范围测量，请描述您的设置和探测点。
如果模拟，请描述您的电路原理图。
Micron LPDDR数据表推荐什么？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
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以下为原文

Somehow when looking at signal integrity, the Micron LPDDR memory interface using LVCMOS18 IO seems not quite that good.

What does "not quite that good" mean?

• Is this based on scope waveform or circuit simulation?
  
• If scope measurement, please describe your setup and probe point.
  
• If simulation, please describe your circuit schematic.
  
• What does the Micron LPDDR datasheet recommend?
  

-- Bob Elkind
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Summary:
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2. Search the forums (and search the web) for similar topics.
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谢谢你的兴趣。
我从一个Hyperlynx boardsim项目开始，但将网络导出到了lineim。
LVCMOS18模型是通过ISE生成的。
Micron LPDDR存储器模型连接到FPGA，后者使用LVCMOS18模型。
内存数据表没有说明应该接口的内容。
尽管这是一个50欧姆路径的直接点对点连接，但信号的两个边缘都显示出明显的毛刺。
这是使用LPDDR驱动FPGA时的情况。
最后我直接在lineim中连接了两个LVCMOS18模型，中间没有任何痕迹。
接收端的仿真波形很像三角波。
高点接近2.3V而不是1.8。
所以现在我想知道模型本身是否有任何问题。
虽然IV曲线看起来很正常。



以下为原文

Thanks for the interest.
 
I started with a Hyperlynx boardsim project but exported the net to linesim.
The LVCMOS18 model was generated through ISE. The Micron LPDDR memory model is connected to the FPGA, which uses the LVCMOS18 model. The memory data sheet didn't say anything about what should be interfaced to.
Eventhough this is a direct point-to-point connection with 50ohm routes, both edges of the signal showed significant glitches. This is when using the LPDDR to drive the FPGA.
Eventually I just hooked up two LVCMOS18 models in linesim directly without any trace in the middle. The simulation waveform at the receiving end showed up much like a triangle wave. The high point is close to 2.3V instead of 1.8.
 
so now I'm wondering if the model itself has any problem. The IV curves do look normal though.

您是否阅读过Micron关于LPDRAM路由和互连的说明？
我想你会发现它们很有趣。
例如，您是在配置DRAM的半强度还是四分之一强度驱动器？
全强度驱动器的输出阻抗为25欧姆 - 驱动器太多，以避免在未端接的50欧姆传输线上振铃。
这是未终止的点对点设计的注释。
好东西在那里！
以下是美光网站上的其余部分。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

Have you read the Micron apnotes for LPDRAM routing and interconnect?  I think you'll find them interesting.
 
For example, are you configuring the DRAM for half-strength or quarter-strength drive?  Full-strength drive is 25-ohm output impedance -- too much drive to avoid ringing on an unterminated 50-ohm transmission line.
 
Here's the apnote for unterminated point-to-point design.  Good stuff in there!  Here are the rest of the apnotes on the Micron website.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

谢谢，鲍勃。
我之前没有看到Micron的应用笔记，但我确实看到了他们不同的驱动强度模型。
我在模拟中尝试了不同的驱动强度，但边缘上的毛刺都存在于所有组合中。
在他们的模拟中，我得到了类似的写操作结果。
写入期间信号非常干净。
读操作是显示此操作的操作。
美光应用笔记中的一个有趣的事情是，虽然它们显示出大量的过度拍摄和振铃，但我看不到边缘有任何毛刺。
我目前正在与Xilinx支持模型上的人员。
我会发布我发现的东西。
非常感谢。



以下为原文

Thanks, Bob.
 
I didn't see the app note from Micron before but I did see their different drive strength models. I did try different drive strength in my simulation but the glitches on the edges are present in all combinations. As in their simulation, I got similar results for the write operations. The signals are quite clean during writes. The read operation is the one showing this.
 
One interesting thing in the Micron app note is that eventhough they showed massive over-shoot and ringing, I don't see any glitch on the edges. I'm currently working with Xilinx support people on the models. I'll post what I find out.
 
Thanks a lot.