我通常使用case语句制作多路复用器，如果一切都符合时间，我就离开它
在那。
当N对于多路复用器而言太大而无法满足时序时，我喜欢创建流水线多级
mux，再次使用case语句。
从理论上讲，综合工具可以搞清楚
怎么做，但我并不总是愿意打开所有必需的旋钮（即注册
重新定时等）。
如果您的问题源于如何描述一般参数化的N输入
在Verilog的mux，我还没有真正考虑过这一点。
Verilog有一些局限性
因为定义描述二维结构的端口并不容易。
它的
很容易参数化输入的宽度，但输入的数量
是另一个问题。
您可能想在comp.lang.verilog上提出问题
看看那里的大师们在想什么。
你可能会从中获得大量的话语
Jonathan Bromley为什么需要VHDL来解决这个问题。
祝你好运，
的Gabor
- Gabor
以上来自于谷歌翻译
以下为原文
I generally make muxes with case statements and if everything meets timing I just leave it
at that.
When N gets too large for the mux to meet timing, I like to create a pipelined multistage
mux, again using case statements. Theoretically the synthesis tools can figure out
how to do this, but I'm not always willing to turn on all the required knobs (i.e. register
retiming, etc.).
If your problem stems from how to describe a general parameterized N-input
mux in Verilog, I haven't really thought about that. Verilog has some limitations
in that it isn't easy to define ports that describe a two-dimensional structure. It's
easy enough to parameterize the width of the inputs, but the number of inputs
is another issue. You may want to pose the question on comp.lang.verilog
to see what the gurus there think. You're likely to get a large discourse from
Jonathan Bromley on why you need VHDL for this.
Good Luck,
Gabor
-- Gabor
我通常使用case语句制作多路复用器，如果一切都符合时间，我就离开它
在那。
当N对于多路复用器而言太大而无法满足时序时，我喜欢创建流水线多级
mux，再次使用case语句。
从理论上讲，综合工具可以搞清楚
怎么做，但我并不总是愿意打开所有必需的旋钮（即注册
重新定时等）。
如果您的问题源于如何描述一般参数化的N输入
在Verilog的mux，我还没有真正考虑过这一点。
Verilog有一些局限性
因为定义描述二维结构的端口并不容易。
它的
很容易参数化输入的宽度，但输入的数量
是另一个问题。
您可能想在comp.lang.verilog上提出问题
看看那里的大师们在想什么。
你可能会从中获得大量的话语
Jonathan Bromley为什么需要VHDL来解决这个问题。
祝你好运，
的Gabor
- Gabor
以上来自于谷歌翻译
以下为原文
I generally make muxes with case statements and if everything meets timing I just leave it
at that.
When N gets too large for the mux to meet timing, I like to create a pipelined multistage
mux, again using case statements. Theoretically the synthesis tools can figure out
how to do this, but I'm not always willing to turn on all the required knobs (i.e. register
retiming, etc.).
If your problem stems from how to describe a general parameterized N-input
mux in Verilog, I haven't really thought about that. Verilog has some limitations
in that it isn't easy to define ports that describe a two-dimensional structure. It's
easy enough to parameterize the width of the inputs, but the number of inputs
is another issue. You may want to pose the question on comp.lang.verilog
to see what the gurus there think. You're likely to get a large discourse from
Jonathan Bromley on why you need VHDL for this.
Good Luck,
Gabor
-- Gabor
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