最大频率太低

你好
我是FPGA项目的初学者，我做了一个项目，但是没有用。
合成过程以最高频率结束：20 MHZ，我的项目需要64 MHZ。
所以我用2个计数器和2个DCM来降低项目，但问题仍然存在。
任何人都可以解释原因吗？
我正在使用斯巴达3E。
它遵循我的代码：
核心
--------------------------------------------------
-------------------------------- library IEEE;使用IEEE.STD_LOGIC_1164.ALL;使用IEEE.STD_LOGIC_ARITH.ALL;使用
IEEE.STD_LOGIC_UNSIGNED.ALL;
----如果在此code.library UNISIM中实例化----任何Xilinx原语，则取消注释以下库声明;使用UNISIM.VComponents.all;
实体核心是端口（clk：在STD_LOGIC中; rst：在std_logic中; led1：输出STD_LOGIC; led2：输出STD_LOGIC）;结束核心;
架构核心的行为是
COMPONENT low_dcmPORT（CLKIN_IN：IN std_logic; RST_IN：IN std_logic; CLKDV_OUT：OUT std_logic; CLKIN_IBUFG_OUT：OUT std_logic; CLK0_OUT：OUT std_logic; LOCKED_OUT：OUT std_logic）; END COMPONENT;
COMPONENT core_dcmPORT（CLKIN_IN：IN std_logic; RST_IN：IN std_logic; CLKFX_OUT：OUT std_logic; LOCKED_OUT：OUT std_logic）; END COMPONENT;
COMPONENT counterPORT（clk：IN std_logic; saida：OUT std_logic）; END COMPONENT;
signal reset_dcm，reset_locked，low_dcm_locked：std_logic; signal clock_6m，clock_4m，clk4mhz，clk_in：std_logic; signal clkin_ibufg，clock_64m，core_dcm_locked，mclk：std_logic;
开始
reset_dcm
Inst_low_dcm：low_dcm PORT MAP（CLKIN_IN => clk，RST_IN => reset_dcm，CLKDV_OUT => clock_4m，CLKIN_IBUFG_OUT => clkin_ibufg，CLK0_OUT => clock_6m，LOCKED_OUT => low_dcm_locked）;
Inst_core_dcm：core_dcm PORT MAP（CLKIN_IN => clkin_ibufg，RST_IN => reset_dcm，CLKFX_OUT => clock_64m，LOCKED_OUT => core_dcm_locked）;
Inst_counter1：计数器端口映射（clk => clock_4m，saida => led1）;
Inst_counter2：计数器端口映射（clk => clock_64m，saida => led2）;
结束行为;
柜台
库IEEE;使用IEEE.STD_LOGIC_1164.ALL;使用IEEE.STD_LOGIC_ARITH.ALL;使用IEEE.STD_LOGIC_UNSIGNED.ALL;
----如果在此代码中实例化----任何Xilinx原语，则取消注释以下库声明.-- library UNISIM;  - 使用UNISIM.VComponents.all;
实体计数器是端口（clk：在STD_LOGIC中;表示：输出STD_LOGIC）;结束计数器;
建筑的行为是
信号计数：std_logic_vector（23 downto 0）;
开始
process（clk）beginif clk ='0'和clk'event thencount end if if; end process;
说最终行为;
合成结果：
时间概要：---------------速度等级：-4
最小周期：50.187ns（最大频率：19.926MHz）时钟前的最小输入到达时间：未找到路径时钟后的最大输出所需时间：4.310ns最大组合路径延迟：未找到路径
我发现当我评论CORE_DCM组件和实例化时，以及COUNTER2实例化项目运行时：
时间概要：---------------速度等级：-4
最小周期：3.137ns（最大频率：318.810MHz）时钟前的最小输入到达时间：未找到路径时钟后的最大输出所需时间：4.310ns最大组合路径延迟：未找到路径
非常感谢。



以下为原文

Hi

I'm a beginner in fpga projects and I have made a project, but it didn't work. The synthesize process ends with maximum frequency very low: 20 MHZ and my project need 64 MHZ. So I made a project lower with 2 counters and 2 DCMs, but problem persists still. Can anybody explain why?
I'm using Spartan 3E.
It follows my code:


THE CORE

----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity core is
    Port ( clk : in  STD_LOGIC;
     rst : in std_logic;
           led1 : out  STD_LOGIC;
           led2 : out  STD_LOGIC);
end core;
architecture Behavioral of core is

COMPONENT low_dcm
PORT(
  CLKIN_IN : IN std_logic;
  RST_IN : IN std_logic;         
  CLKDV_OUT : OUT std_logic;
  CLKIN_IBUFG_OUT : OUT std_logic;
  CLK0_OUT : OUT std_logic;
  LOCKED_OUT : OUT std_logic
  );
END COMPONENT;

COMPONENT core_dcm
PORT(
  CLKIN_IN : IN std_logic;
  RST_IN : IN std_logic;         
  CLKFX_OUT : OUT std_logic;
  LOCKED_OUT : OUT std_logic
  );
END COMPONENT;

COMPONENT counter
PORT(
  clk : IN std_logic;         
  saida : OUT std_logic
  );
END COMPONENT;
signal reset_dcm, reset_locked, low_dcm_locked : std_logic;
signal clock_6m, clock_4m, clk4mhz, clk_in : std_logic;
signal clkin_ibufg, clock_64m, core_dcm_locked, mclk : std_logic;

begin
reset_dcm <= '1' when rst = '1' else '0';

Inst_low_dcm: low_dcm PORT MAP(
  CLKIN_IN => clk,
  RST_IN => reset_dcm,
  CLKDV_OUT => clock_4m,
  CLKIN_IBUFG_OUT => clkin_ibufg,
  CLK0_OUT => clock_6m,
  LOCKED_OUT => low_dcm_locked
);

Inst_core_dcm: core_dcm PORT MAP(
  CLKIN_IN => clkin_ibufg,
  RST_IN => reset_dcm,
  CLKFX_OUT => clock_64m,
  LOCKED_OUT => core_dcm_locked
);

Inst_counter1: counter PORT MAP(
  clk => clock_4m,
  saida => led1
);

Inst_counter2: counter PORT MAP(
  clk => clock_64m,
  saida => led2
);

end Behavioral;


THE COUNTER

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity counter is
    Port ( clk : in  STD_LOGIC;
           saida : out  STD_LOGIC);
end counter;
architecture Behavioral of counter is
signal count : std_logic_vector (23 downto 0);
begin
  process (clk)
  begin
   if clk = '0' and clk'event then
    count <= count + 1;
   end if;
  end process;
  saida <= count(23);
end Behavioral;




SYNTHESIZE RESULTS:


Timing Summary:
---------------
Speed Grade: -4
   Minimum period: 50.187ns (Maximum Frequency: 19.926MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 4.310ns
   Maximum combinational path delay: No path found


I discovered that when I comment CORE_DCM component and instantiation, and COUNTER2 instantiation the project run at:

Timing Summary:
---------------
Speed Grade: -4
   Minimum period: 3.137ns (Maximum Frequency: 318.810MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 4.310ns
   Maximum combinational path delay: No path found


Thanks so much.