嗨巴里，
关于这一点只是一些想法。
您可能需要考虑使用同步SRAM而不是异步。
一。
用异步。
SRAM，你
需要记住的是，您的总访问时间是地址线的时钟输出时间+ SRAM的访问时间+电线延迟+
使用驱动访问的时钟在FPGA中捕获数据所需的设置时间。
新的内存接口可能会相当混乱
到FPGA设计:-)。
同步SRAM通常是流水线的，因此访问在多个时钟周期内被分解。
您的吞吐量保持不变，但是
延迟增加（仅2或3个周期）。
就你的逻辑而言，你只需在特定的时钟周期发出你的读取请求......你会
我知道数据可以在几个周期之后被捕获。
此外，如果您布置电路板使所有信号都跟踪匹配，
您可以使用FPGA中的一个功能来扭曲存储器的时钟，从而实际上消除延迟，从而使您的存储器接口更加强大。
那里
还可以使用其他功能，具体取决于FPGA如何通过对所用内存的重新计时来实现。
另一件事......如果你需要在writedata到达时准备你的记忆（即你的记忆内容随着时间的推移而变化），那么它可能是可能的
使用同步RAM要容易一些，因为您可以更轻松地安排所有交易（即将它们排队并将它们计时）。
当你
必须驱动异步。
RAM，实际上，您必须自己创建此同步层。
对不起，如果我在这里混淆。
虽然是异步的。
记忆将工作得很好，只是可能会有一些隐藏的陷阱会让你感到沮丧
你是这个东西的新手:-)。
同步方法将有助于缓解其中一些问题。
大多数同步RAM可能会花费更多，但我认为
如果设计不是非常*成本很有意义，那么这是一个更好的设计决策。
埃德
以上来自于谷歌翻译
以下为原文
Hi Barry,
Just a few thoughts on this. You might want to consider using a synchronous SRAM as opposed to an async. one. With async. SRAM, you
need to keep in mind that your total access time is the clock-to-out of your address lines + the access time of the SRAM + the wire delays + the
setup time required to capture data in the FPGA using the clock that drives the access. Memory interfacing can get fairly confusing when new
to FPGA design :-).
Synchronous SRAMs are typically pipelined, so the access is broken up on multiple clock cycles. Your throughput stays about the same, but
there is an increase in latency (only 2 or 3 cycles). In terms of your logic, you'd simply issue your read request on a particular clock cycles...you'd
know that data would be available for capture a couple of cycles later. Moreover, if you layout your board such that all of your signals are trace matched,
you could use a feature in the FPGA to skew the memory's clock to virtually remove delays thus making your memory interface a heck of a lot more robust. There
are also other features you can use depending on how your FPGA is clocked with resepct to the memory being used.
One other thing....if you need to read your memory while write data is arriving (i.e. the contents of your memory is going to change over time), it would proabably
be a bit easier to use a synchronous RAM since you can schedule all of your transactions a bit easier (i.e. queue them up and clock them out). When you
have to drive an async. RAM, you, in effect, have to create this synchronization layer yourself.
Sorry if I am being confusing here. While an async. memory will work just fine, its just that there might be a few hidden gotchas that will frustrate you if
you are new to this stuff :-). A synchronous approach will help to alleviate some of these issues. Most synchronous RAMs may cost a bit more, but I think it
is a better design decision if the design is not *extremely* cost concious.
Ed
嗨巴里，
关于这一点只是一些想法。
您可能需要考虑使用同步SRAM而不是异步。
一。
用异步。
SRAM，你
需要记住的是，您的总访问时间是地址线的时钟输出时间+ SRAM的访问时间+电线延迟+
使用驱动访问的时钟在FPGA中捕获数据所需的设置时间。
新的内存接口可能会相当混乱
到FPGA设计:-)。
同步SRAM通常是流水线的，因此访问在多个时钟周期内被分解。
您的吞吐量保持不变，但是
延迟增加（仅2或3个周期）。
就你的逻辑而言，你只需在特定的时钟周期发出你的读取请求......你会
我知道数据可以在几个周期之后被捕获。
此外，如果您布置电路板使所有信号都跟踪匹配，
您可以使用FPGA中的一个功能来扭曲存储器的时钟，从而实际上消除延迟，从而使您的存储器接口更加强大。
那里
还可以使用其他功能，具体取决于FPGA如何通过对所用内存的重新计时来实现。
另一件事......如果你需要在writedata到达时准备你的记忆（即你的记忆内容随着时间的推移而变化），那么它可能是可能的
使用同步RAM要容易一些，因为您可以更轻松地安排所有交易（即将它们排队并将它们计时）。
当你
必须驱动异步。
RAM，实际上，您必须自己创建此同步层。
对不起，如果我在这里混淆。
虽然是异步的。
记忆将工作得很好，只是可能会有一些隐藏的陷阱会让你感到沮丧
你是这个东西的新手:-)。
同步方法将有助于缓解其中一些问题。
大多数同步RAM可能会花费更多，但我认为
如果设计不是非常*成本很有意义，那么这是一个更好的设计决策。
埃德
以上来自于谷歌翻译
以下为原文
Hi Barry,
Just a few thoughts on this. You might want to consider using a synchronous SRAM as opposed to an async. one. With async. SRAM, you
need to keep in mind that your total access time is the clock-to-out of your address lines + the access time of the SRAM + the wire delays + the
setup time required to capture data in the FPGA using the clock that drives the access. Memory interfacing can get fairly confusing when new
to FPGA design :-).
Synchronous SRAMs are typically pipelined, so the access is broken up on multiple clock cycles. Your throughput stays about the same, but
there is an increase in latency (only 2 or 3 cycles). In terms of your logic, you'd simply issue your read request on a particular clock cycles...you'd
know that data would be available for capture a couple of cycles later. Moreover, if you layout your board such that all of your signals are trace matched,
you could use a feature in the FPGA to skew the memory's clock to virtually remove delays thus making your memory interface a heck of a lot more robust. There
are also other features you can use depending on how your FPGA is clocked with resepct to the memory being used.
One other thing....if you need to read your memory while write data is arriving (i.e. the contents of your memory is going to change over time), it would proabably
be a bit easier to use a synchronous RAM since you can schedule all of your transactions a bit easier (i.e. queue them up and clock them out). When you
have to drive an async. RAM, you, in effect, have to create this synchronization layer yourself.
Sorry if I am being confusing here. While an async. memory will work just fine, its just that there might be a few hidden gotchas that will frustrate you if
you are new to this stuff :-). A synchronous approach will help to alleviate some of these issues. Most synchronous RAMs may cost a bit more, but I think it
is a better design decision if the design is not *extremely* cost concious.
Ed
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