@wpravinyou可以编写一个verilog任务，它读取现有文件，重新排列数据并“强制”信号进入bram以高速加载它们，然后“释放”并让模拟运行。
- 如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。
以上来自于谷歌翻译
以下为原文
@wpravin you can write a verilog task which reads the existing file, re-arrange the data and "force" signals into the bram to load them at a high speed, then "release" and let the simulation run.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
@wpravinyou可以编写一个verilog任务，它读取现有文件，重新排列数据并“强制”信号进入bram以高速加载它们，然后“释放”并让模拟运行。
- 如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。
以上来自于谷歌翻译
以下为原文
@wpravin you can write a verilog task which reads the existing file, re-arrange the data and "force" signals into the bram to load them at a high speed, then "release" and let the simulation run.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
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