寻求为FIR滤波器实现无乘法器的乘法器

大家好，如果这是错误的论坛，请道歉，如果有人指向正确的论坛，我将不胜感激。
免责声明：我是VHDL的新手。
我正在寻求为FIR滤波器实现无乘法器的乘法器。
我想尽可能地做到一般，所以我不想硬编码我的组件展示位置。
是否有一种程序生成组件的好方法（即乘数）？
我在CSD中编码了常数被乘数的数字，并将其存储为字符串，我通过'generic'语句将其传递给组件。
现在我试图使用生成循环（循环遍历字符串）来放置加法器，减法器和移位器。
问题是一个加法器/减法器的输出直接输入到下一个输入器的输入端，由于存在未知数量的加法器，我不能事先声明信号。
最好的方法是什么？

以上来自于谷歌翻译

以下为原文

Hi all, apologies if this is the wrong forum for this, it would be much appreciated if someone could point toward the right one.

Disclaimer: I'm new to VHDL.

I'm looking to implement a multiplier-less multiplier for an FIR filter. I'm trying to be as general as possible, so I don't want to hard-code my component placements. Is there a good method of procedurally generating a component (i.e. a multiplier)? I've encoded the digits of the constant multiplicand in CSD and stored it as string which I'm passing into the component via a 'generic' statement. Now I'm attempting to use a generate loop (looping over the string) to place adders, subtractors, and shifters. The issue is that the output of one adder/subtractor is piped directly into the input of the next one and since there is an unknown amount of adders, I can't declare the signals before hand. What's the best way to go about this?

陈鲜孰

2019-4-19 07:14:06

您可以使用数组声明“通用”数量的信号。
如果每个阶段都有共同的信号，则记录数组会有所帮助。
即：
输入my_signals是记录
i，q：签名（31 downto 0）;
结束记录;
type my_signal_array是my_signals的数组（自然范围）;
signal z：my_signal_array（0到GENERIC_VALUE）;
.....
z（0）.I clk，real_in => z（n）.i，imag_in = z（n）.q，real_out => z（n + 1）.I，imag_out => z（n + 1）.q
）;
结束生成;
use_block_B：如果不是use_block_A生成
INST：BLOCK_B（clk => clk，real_in => z（n）.i，imag_in = z（n）。q，real_out => z（n + 1）.I，imag_out => z（n + 1）。
q）;
结束生成;
结束生成; I_out q_out
无论如何，这是个主意。
“z”信号在体系结构中声明（不在生成内部），因此它对生成块是全局的。

以上来自于谷歌翻译

以下为原文

You can declare a "generic" number of signals using arrays. An array of records helps if there are common bundle of signals for each stage. i.e.:
type my_signals is record i,q : signed(31 downto 0);end record;type my_signal_array is array(natural range <>) of my_signals;signal z : my_signal_array(0 to GENERIC_VALUE);.....z(0).I <= some_input..;z(0).q <= some_input...; stages : for n in z'range generatebegin use_block_A : if use_block_A generate INST : BLOCK_A ( clk => clk, real_in => z(n).i, imag_in = z(n).q , real_out => z(n+1).I , imag_out => z(n+1).q ); end generate;
use_block_B : if not use_block_A generate INST : BLOCK_B ( clk => clk, real_in => z(n).i, imag_in = z(n).q , real_out => z(n+1).I , imag_out => z(n+1).q ); end generate;end generate;

I_out <= z(GENERIC_VALUE).I;
q_out <= z(GENERIC_VALUE).q;
Anyway that's the idea. The "z" signal is declared in the architecture (not inside the generate), so that it is global to the generate blocks.