HIN一个带有中断嵌套的DSSPICEPXXXMC204。假设CPU在发生较低中断时正在处理更高优先级的ISR。可以堆叠多少个int?有7个优先级,这是否意味着有可能“堆叠”7个中断级别,而更高级别的中断呢?在数据表/附录中我不清楚(至少对我来说不清楚),在我读的一些
论坛中,只有2个可能的中断同时使用优先级级别(7)来解决冲突。基本上我想知道DSPIC是否提供了7级嵌套中断(由PRORIRTE解决)。Y)或只有2个嵌套级别(高/低),但不同来源之间的冲突由优先级来解决。注意:我的朋友想要/需要知道这一点,但是他访问论坛的确认
电子邮件花费了很长时间。所以我在他的欢呼声中写作。
以上来自于百度翻译
以下为原文
Hi
in a dsPIC33EPXXXMC204 with interrupt nes
ting enabled. Suppose the CPU is processing an higher priority ISR when an lower interrupt occurs. how many levels of int can be stacked ? With 7 priority levels, does it mean there is possible to "stack" 7 levels of interrupts, with the higher interrupting the others?
It's not clear in the datasheet/appnotes i read (at least not clear to me), and in some forums I read there is only 2 possible interrupts at the same time and priority level (7) are used to solve the conflict.
Basically I want to know if dsPIC provide 7 levels of nested interrupts (solved by priority) or only 2 nested levels (high/low) but with conflicts between different sources solved by priority level.
Note: a friend of mine wants/needs to know this but his confirmation email to access the forum is taking ages.. so i'm writing in his behalf
Cheers.