我的建议是聘请一位经验丰富的FPGA顾问来指导您完成这项工作。
作为@ eilertsaid，SimuLink生成的HDL代码可能远非最佳时序或资源方面。
经验丰富的FPGA设计人员可以以更优化的方式将您的Matlab / SimuLink代码映射到硬件，从而使其更小并且能够更快地运行。
Virtex-6中的200MHz应该是非常可行的。
我在这里假设你的时钟受到了适当的限制，并且工具无法进行计时。
如果你没有时钟限制，那么这就是开始的地方。
以上来自于谷歌翻译
以下为原文
My advice would be to hire an experienced FPGA consultant to walk you through this. As @eilert said, HDL code generated by SimuLink could be far from optimal timing-wise or resource-wise. An experienced FPGA designer could map your Matlab/SimuLink code to hardware in a much more optimal way that makes it smaller and able to run faster. 200MHz in a Virtex-6 should be very doable.
I'm assuming here that you have your clock constrained properly and that the tools just can't make timing. If you don't have your clocks constrained then that's the place to start.
我的建议是聘请一位经验丰富的FPGA顾问来指导您完成这项工作。
作为@ eilertsaid，SimuLink生成的HDL代码可能远非最佳时序或资源方面。
经验丰富的FPGA设计人员可以以更优化的方式将您的Matlab / SimuLink代码映射到硬件，从而使其更小并且能够更快地运行。
Virtex-6中的200MHz应该是非常可行的。
我在这里假设你的时钟受到了适当的限制，并且工具无法进行计时。
如果你没有时钟限制，那么这就是开始的地方。
以上来自于谷歌翻译
以下为原文
My advice would be to hire an experienced FPGA consultant to walk you through this. As @eilert said, HDL code generated by SimuLink could be far from optimal timing-wise or resource-wise. An experienced FPGA designer could map your Matlab/SimuLink code to hardware in a much more optimal way that makes it smaller and able to run faster. 200MHz in a Virtex-6 should be very doable.
I'm assuming here that you have your clock constrained properly and that the tools just can't make timing. If you don't have your clocks constrained then that's the place to start.
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