建议：使用PCI总线方法进行时钟分配。
时钟发生器为每个人提供总线时钟的副本，包括主设备。
时钟发生器的输出（通过构造）完全相位对齐。
从发生器到每个从设备（和主设备）的传输路径被构造成相等的长度，因此PCI总线上的每个“方”接收与所有其他PCI总线“各方”相位对准的时钟。
这意味着您的FPGA充当“主”（AND作为时钟发生器）生成两个相同时间的时钟输出副本。
一个副本转到从FPGA，另一个副本返回主FPGA。
两个时钟互连构造成在长度和结构上相同，因此互连不会导致两个时钟之间的偏斜。
这有意义吗？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。
以上来自于谷歌翻译
以下为原文
Suggestion: use the PCI bus approach to clock distribution. The clock generator provides a copy of the bus clock for everyone, including the master. The clock generator's outputs are (by construction) perfectly phase aligned. The transmission paths from the generator to each of the slaves (and masters) are constructed to be equal length, and so each 'party' on the PCI bus receives a clock which is phase aligned with all the other PCI bus 'parties'.
This means that your FPGA acting as 'master' (AND as clock generator) generates two identically timed output copies of the clock. One copy goes to the slave FPGA, and the other copy is returned to the master FPGA. The two clock interconnects are constructed to be identical in length and construction, so the interconnect does not contribute to skew between the two clocks.
Does this make sense?
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369
Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
建议：使用PCI总线方法进行时钟分配。
时钟发生器为每个人提供总线时钟的副本，包括主设备。
时钟发生器的输出（通过构造）完全相位对齐。
从发生器到每个从设备（和主设备）的传输路径被构造成相等的长度，因此PCI总线上的每个“方”接收与所有其他PCI总线“各方”相位对准的时钟。
这意味着您的FPGA充当“主”（AND作为时钟发生器）生成两个相同时间的时钟输出副本。
一个副本转到从FPGA，另一个副本返回主FPGA。
两个时钟互连构造成在长度和结构上相同，因此互连不会导致两个时钟之间的偏斜。
这有意义吗？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。
以上来自于谷歌翻译
以下为原文
Suggestion: use the PCI bus approach to clock distribution. The clock generator provides a copy of the bus clock for everyone, including the master. The clock generator's outputs are (by construction) perfectly phase aligned. The transmission paths from the generator to each of the slaves (and masters) are constructed to be equal length, and so each 'party' on the PCI bus receives a clock which is phase aligned with all the other PCI bus 'parties'.
This means that your FPGA acting as 'master' (AND as clock generator) generates two identically timed output copies of the clock. One copy goes to the slave FPGA, and the other copy is returned to the master FPGA. The two clock interconnects are constructed to be identical in length and construction, so the interconnect does not contribute to skew between the two clocks.
Does this make sense?
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369
Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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