保罗，
亚稳定性不是世界末日。
如果信号很重要（您必须知道它是零还是一个），则需要同步器。
阶段的数量仅使亚稳态的发生频率降低（它永远不会完全消失）。
一个很好的例子是键盘：如果你键入并获得错误的字符，你可以退格，并输入正确的字符。
不需要额外的阶段。
键入的异步性质和系统采样对于偶尔的亚稳状态是好的，并且字符不想要你想要的（因为打碎的位从未稳定，并且产生了一些随机字符）。
不能容忍亚稳态的情况的一个很好的例子是FIFO中的满标志和空标志。
输入上的时钟正在填充FIFO，输出上的时钟正在清空FIFO。
如果满标志变为亚稳态，则可能会尝试将FIFO填满过满（丢失一个值），或者您可能认为FIFO已满，而不是。
对于这种情况，同步器是强制性的良好工程。
通常，满标志几乎已满（一个或多个比实际完全少），以使FIFO在您的设计中更加健壮。
因此发生亚稳态信号。
仅仅因为它可能是'避免它是糟糕的工程。
同步器可以在需要它们的地方使用，并且它的亚稳定频率很重要。
同步器不能消除亚稳态，它只会降低发生率。
Austin Lesea主要工程师Xilinx San Jose
在原帖中查看解决方案
以上来自于谷歌翻译
以下为原文
Paul,
Metastability is not the end of the world. If the signal is important (you must know if it is zero or one) then a synchronizer is required. The number of stages only makes the occurence of the metastable condition less frequent (it never goes away completely).
A good example is of a keyboard: if you type and get the wrong character, you back-space, and type the right one. No extra stages are required. The asynchrnous nature of typing, and the system sampling is just fine with the occasional metastable state, and the character being not want you wanted (because the smapled bits never stabalized, and some random character resulted).
A good example of a case where metastability is not to be tolerated is in a FIFO for the full, and empty flags. The clock on the input is filling the FIFO, the clock on the output is emptying the FIFO. If the full flag goes metastable, you might try to fill the FIFO to over-full (lose a value), or you might think the FIFO is full, when it isn't. For this case, the synchronizer is mandatory good engineering. Often, the full flag is almost full (one or more less than really full), to make the FIFO more robust in your design.
So a signal being metastable happens. Avoiding it just because it 'might be' is poor engineering. Synchronizers get used where they are needed, and how often it goes metastable is important. The synchronizer does not eliminate metastability, it only reduces the occurence rate.
Austin Lesea
Principal Engineer
Xilinx San JoseView solution in original post
保罗，
亚稳定性不是世界末日。
如果信号很重要（您必须知道它是零还是一个），则需要同步器。
阶段的数量仅使亚稳态的发生频率降低（它永远不会完全消失）。
一个很好的例子是键盘：如果你键入并获得错误的字符，你可以退格，并输入正确的字符。
不需要额外的阶段。
键入的异步性质和系统采样对于偶尔的亚稳状态是好的，并且字符不想要你想要的（因为打碎的位从未稳定，并且产生了一些随机字符）。
不能容忍亚稳态的情况的一个很好的例子是FIFO中的满标志和空标志。
输入上的时钟正在填充FIFO，输出上的时钟正在清空FIFO。
如果满标志变为亚稳态，则可能会尝试将FIFO填满过满（丢失一个值），或者您可能认为FIFO已满，而不是。
对于这种情况，同步器是强制性的良好工程。
通常，满标志几乎已满（一个或多个比实际完全少），以使FIFO在您的设计中更加健壮。
因此发生亚稳态信号。
仅仅因为它可能是'避免它是糟糕的工程。
同步器可以在需要它们的地方使用，并且它的亚稳定频率很重要。
同步器不能消除亚稳态，它只会降低发生率。
Austin Lesea主要工程师Xilinx San Jose
在原帖中查看解决方案
以上来自于谷歌翻译
以下为原文
Paul,
Metastability is not the end of the world. If the signal is important (you must know if it is zero or one) then a synchronizer is required. The number of stages only makes the occurence of the metastable condition less frequent (it never goes away completely).
A good example is of a keyboard: if you type and get the wrong character, you back-space, and type the right one. No extra stages are required. The asynchrnous nature of typing, and the system sampling is just fine with the occasional metastable state, and the character being not want you wanted (because the smapled bits never stabalized, and some random character resulted).
A good example of a case where metastability is not to be tolerated is in a FIFO for the full, and empty flags. The clock on the input is filling the FIFO, the clock on the output is emptying the FIFO. If the full flag goes metastable, you might try to fill the FIFO to over-full (lose a value), or you might think the FIFO is full, when it isn't. For this case, the synchronizer is mandatory good engineering. Often, the full flag is almost full (one or more less than really full), to make the FIFO more robust in your design.
So a signal being metastable happens. Avoiding it just because it 'might be' is poor engineering. Synchronizers get used where they are needed, and how often it goes metastable is important. The synchronizer does not eliminate metastability, it only reduces the occurence rate.
Austin Lesea
Principal Engineer
Xilinx San JoseView solution in original post
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