Datasheet P32/37
SERIAL INTERFACE
Figure 50 shows
the timing diagram for the serial interface of the AD7321.(可以软件模拟操作时序，控制好/CS,SCLK,DIN,然后在特定的时刻，读取DOUT即可)
The CS signal
initiates the data transfer and the conversion process.
The falling edge of CS puts the track-and-hold into hold mode and takes the bus out of three-state. Then the analog input signal is sampled. Once the conversion is initiated, it requires
16 SCLK cycles to complete.
The track-and-hold goes back into track mode on the
14th SCLK rising edge. On the
16th SCLK falling edge, the DOUT line returns to three-state（这个时候，Dout数据有效）.
可以用示波器/逻辑分析仪，挂出这4根线看操作时序还对。
Datasheet P32/37
SERIAL INTERFACE
Figure 50 shows the timing diagram for the serial interface of the AD7321.(可以软件模拟操作时序，控制好/CS,SCLK,DIN,然后在特定的时刻，读取DOUT即可)
The CS signal initiates the data transfer and the conversion process.
The falling edge of CS puts the track-and-hold into hold mode and takes the bus out of three-state. Then the analog input signal is sampled. Once the conversion is initiated, it requires 16 SCLK cycles to complete.
The track-and-hold goes back into track mode on the 14th SCLK rising edge. On the 16th SCLK falling edge, the DOUT line returns to three-state（这个时候，Dout数据有效）.
可以用示波器/逻辑分析仪，挂出这4根线看操作时序还对。
举报
