顶层程序负责连接
仿真程序的各个部分:模拟 PHY 程序、模拟主机程序和以太网控制程序。同时顶层程序需要控制仿真的进行,主要代码如下:
- `include "eth_phy_defines.v"
- `include "wb_model_defines.v"
- `include "tb_eth_defines.v"
- `include "eth_defines.v"
- `include "timescale.v"
- module tb_ethernet();
- //寄存器与连线
- reg wb_clk;
- ……
- //连接以太网控制器
- eth_top eth_top
- (
- .wb_clk_i(wb_clk), .wb_rst_i(wb_rst),
- .wb_adr_i(eth_sl_wb_adr_i[11:2]), .wb_sel_i(eth_sl_wb_sel_i), .wb_we_i(eth_sl_wb_we_i
- ),
- .wb_cyc_i(eth_sl_wb_cyc_i), .wb_stb_i(eth_sl_wb_stb_i), .wb_ack_o(eth_sl_wb_ack
- _o),
- .wb_err_o(eth_sl_wb_err_o), .wb_dat_i(eth_sl_wb_dat_i), .wb_dat_o(eth_sl_wb_dat
- _o),
- .m_wb_adr_o(eth_ma_wb_adr_o), .m_wb_sel_o(eth_ma_wb_sel_o), .m_wb_we_o(eth_ma_wb_we
- _o), .m_wb_dat_i(eth_ma_wb_dat_i), .m_wb_dat_o(eth_ma_wb_dat_o), .m_wb_cyc_o(eth_ma_wb_cyc
- _o),
- .m_wb_stb_o(eth_ma_wb_stb_o), .m_wb_ack_i(eth_ma_wb_ack_i), .m_wb_err_i(eth_ma_wb_e
- rr_i),
- //发送数据
- .mtx_clk_pad_i(mtx_clk), .mtxd_pad_o(MTxD), .mtxen_pad_o(MTxEn), .mtxerr_pad_o(MTxErr),
- //接收数据部分
- .mrx_clk_pad_i(mrx_clk), .mrxd_pad_i(MRxD), .mrxdv_pad_i(MRxDV), .mrxerr_pad_i(MRxErr),
- .mcoll_pad_i(MColl), .mcrs_pad_i(MCrs),
- //媒体无关接口模块
- .mdc_pad_o(Mdc_O), .md_pad_i(Mdi_I), .md_pad_o(Mdo_O), .md_padoe_o(Mdo_OE),
- .int_o(wb_int)
- );
- //连接模拟 PHY 部分
- assign Mdio_IO = Mdo_OE ? Mdo_O : 1'bz ;
- assign Mdi_I = Mdio_IO;
- integer phy_log_file_desc;
- eth_phy eth_phy
- (
- .m_rst_n_i(!wb_rst),
- // MAC 发送数据
- .mtx_clk_o(mtx_clk), .mtxd_i(MTxD), .mtxen_i(MTxEn), .mtxerr_i(MTxErr),
- // MAC 接收数据
- .mrx_clk_o(mrx_clk), .mrxd_o(MRxD), .mrxdv_o(MRxDV), .mrxerr_o(MRxErr),
- .mcoll_o(MColl), .mcrs_o(MCrs),
- //媒体无关接口模块
- .mdc_i(Mdc_O), .md_io(Mdio_IO),
- .phy_log(phy_log_file_desc)
- );
- // 连接主机模块
- integer host_log_file_desc;
- WB_MASTER_BEHAVIORAL wb_master
- (
- .CLK_I(wb_clk),
- .RST_I(wb_rst),
- .TAG_I({`WB_TAG_WIDTH{1'b0}}),
- .TAG_O(),
- .ACK_I(eth_sl_wb_ack_o),
- .ADR_O(eth_sl_wb_adr), // only eth_sl_wb_adr_i[11:2] used
- .CYC_O(eth_sl_wb_cyc_i),
- .DAT_I(eth_sl_wb_dat_o),
- .DAT_O(eth_sl_wb_dat_i),
- .ERR_I(eth_sl_wb_err_o),
- .RTY_I(1'b0), // inactive (1'b0)
- .SEL_O(eth_sl_wb_sel_i),
- .STB_O(eth_sl_wb_stb_i),
- .WE_O (eth_sl_wb_we_i),
- .CAB_O() // NOT USED for now!
- );
- assign eth_sl_wb_adr_i = {20'h0, eth_sl_wb_adr[11:2], 2'h0};
- ……
- //初始化
- initial
- begin
- //复位信号
- wb_rst = 1'b1;
- #423 wb_rst = 1'b0;
- //清除存储器内容
- clear_memories;
- clear_buffer_descriptors;
- #423 StartTB = 1'b1;
- end
- //产生时钟信号
- initial
- begin
- wb_clk=0;
- forever #15 wb_clk = ~wb_clk; // 2*10 ns -> 33.3 MHz
- end
- integer tests_successfull;
- integer tests_failed;
- reg [799:0] test_name; // used for tb_log_file
- reg [3:0] wbm_init_waits; // initial wait cycles between CYC_O and STB_O of WB Master
- reg [3:0] wbm_subseq_waits; // subsequent wait cycles between STB_Os of WB Master
- reg [2:0] wbs_waits; // wait cycles befor WB Slave responds
- reg [7:0] wbs_retries; // if RTY response, then this is the number of retries before ACK
- reg wbm_working; // tasks wbm_write and wbm_read set signal when working and reset
- it when stop working
- //开始测试内容
- initial
- begin
- wait(StartTB); // 开始测试
- //初始化全局变量
- tests_successfull = 0;
- tests_failed = 0;
- wbm_working = 0;
- wbm_init_waits = 4'h1;
- wbm_subseq_waits = 4'h3;
- wbs_waits = 4'h1;
- wbs_retries = 8'h2;
- wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
- //测试的各个任务
- test_note("PHY generates ideal Carrier sense and Collision signals for following tests");
- eth_phy.carrier_sense_real_delay(0);
- test_mac_full_duplex_transmit(0, 21); //测试全双工方式下传输数据
- test_mac_full_duplex_receive(0, 13); //测试全双工方式下接收数据
- test_mac_full_duplex_flow_control(0, 4); // 测试整个数据流程
- test_note("PHY generates 'real delayed' Carrier sense and Collision signals for following
- tests");
- eth_phy.carrier_sense_real_delay(1);
- // 结束测试
- test_summary;
- $stop;
- end
测试内容通过多个测试任务来执行。